Design Of A Low Voltage,Low Drop-Out (Ldo) Voltage Cmos Regulator

Abstract

In this paper a low voltage, low drop-out (LDO) voltage regulator design procedure is proposed and implemented using 0.25 micron CMOS process. It discusses a 3 to 5V, 50mA CMOS low drop-out linear voltage regulator with a single compensation capacitor of 1pF. The experimental results show that the maximum output load current is 50mA and the regulated output voltage is 2.8V.The regulator provides a full load transient response with less than 5mV overshoots and undershoots. The active layout area is 358.28um × 243.30um.