Low-density Parity-check Decoder Research Articles

An Improved EPA-Based Receiver Design for Uplink LDPC Coded SCMA System

Sparse code multiple access (SCMA) is an emerging paradigm for efficient enabling of massive connectivity in future machine-type communications (MTC). In this letter, we conceive the uplink transmissions of the low-density parity check (LDPC) coded SCMA system. Traditional receiver design of LDPC-SCMA system, which is based on message passing algorithm (MPA) for multiuser detection followed by individual LDPC decoding, may suffer from the drawback of the high complexity and large decoding latency, especially when the system has large codebook size and/or high overloading factor. To address this problem, we introduce a novel receiver design by applying the expectation propagation algorithm (EPA) to the joint detection and decoding (JDD) involving an aggregated factor graph of LDPC code and sparse codebooks. Our numerical results demonstrate the superiority of the proposed EPA based JDD receiver over the conventional Turbo receiver in terms of both significantly lower complexity and faster convergence rate without noticeable error rate performance degradation.

Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard

As the low-density parity-check (LDPC) code has a powerful error-correcting performance and can achieve high throughput, it is being used in many application areas and recently adopted as a channel coding method in the 5G New-Radio communication standard. Unlike other LDPC codes, the 5G LDPC code has various irregular lifting sizes to support diverse message lengths. To meet the demanding requirements of the 5G standard, many solutions have been presented, but all of them are either impractical or fail to satisfy all the requirements. This paper, for the first time, proposes an area-efficient QC-LDPC decoder that satisfies the peak throughput requirements of the 5G standard and supports all the lifting sizes specified in the 5G standard. Instead of relying on full parallelism like in the previous works, this work tries partial parallelism to mitigate the hardware complexity, which leads to high efficiency in hardware complexity. In addition, a novel memory access scheduling method is proposed to solve the data access and alignment problems caused by the partially parallel structure, which is effective in supporting all the lifting sizes. A LDPC decoder realized in 65-nm CMOS technology demonstrates that its decoding throughput is greater than 20Gbps and its area is smaller than the existing decoders.

Decoding of Decode and Forward (DF) Relay Protocol using Min-Sum Based Low Density Parity Check (LDPC) System

Decoding high complexity is a major issue to design a decode and forward (DF) relay protocol. Thus, the establishment of low complexity decoding system would beneficial to assist decode and forward relay protocol. This paper reviews existing methods for the min-sum based LDPC decoding system as the low complexity decoding system. Reference lists of chosen articles were further reviewed for associated publications. This paper introduces comprehensive system model representing and describing the methods developed for LDPC based for DF relay protocol. It is consists of a number of components: (1) encoder and modulation at the source node, (2) demodulation, decoding, encoding and modulation at relay node, and (3) demodulation and decoding at the destination node. This paper also proposes a new taxonomy for min-sum based LDPC decoding techniques, highlights some of the most important components such as data used, result performances and profiles the Variable and Check Node (VCN) operation methods that have the potential to be used in DF relay protocol. Min-sum based LDPC decoding methods have the potential to provide an objective measure the best tradeoff between low complexities decoding process and the decoding error performance, and emerge as a cost-effective solution for practical application.

Implementation of real-time high-speed ultrasound communications through tissue

In this work, we propose a novel implementation of both a transmitter and receiver with field programmable gate arrays (FPGAs) to achieve real-time continuous high-definition (HD) video transmission through tissue, which can enable HD and higher frame rate wireless capsule endoscopy. We used a Texas Instruments AFE58JD48EVM 16 channel analog front end (AFE) evaluation board as the receiver connected to a Xilinx ZCU106 Zynq Ultrascale MPSoC development board in which we implemented a digital down converter (DDC), OFDM demodulator, maximum ratio combiner and low-density parity-check (LDPC) decoder. For the transmitter, we used an Analog Devices EVAL-AD9166 vector signal generator evaluation board, which has a built-in 4.3 dBm output power amplifier as a transmitter connected to another ZCU106 development board in which we implemented a LDPC encoder, OFDM modulator and digital up converter (DUC). The modulated signal was transmitted through a tissue-mimicking abdominal phantom using a 2-mm microcrystal transducer and received with a Sonic Concepts IP103 64 channel phased array at a center frequency of 3.2 MHz. We achieved the continuous transmission of up to over[OML1] 6 Mbps error free payload data rate after LDPC decoder which is used to carry HD video streams through ultrasound.

Improved Recording Performance With Writer Design and Joint Learning-Based Neural Network for Heat-Assisted Interlaced Magnetic Recording

Heat-assisted interlaced magnetic recording (HIMR) further increases the areal density with the interlaced track layout architecture compared to conventional heat-assisted magnetic recording. However, besides the 2-D inter-symbol interference (ISI) and thermal jitters, the transition curvatures due to the circular thermal profile cause severe erasures after write and obvious nonlinear distortions of readback signals. This deteriorates the recording performance severely. Especially the degrees of transition curvatures for the low temperature written track (LT) and high temperature written track (HT) are distinct, which makes the correction of transition curvature with only the writer design impossible. Correspondingly, a comprehensive method consisting of writer design and multitrack detection algorithm with joint learning-based neural network (JLNN) is proposed to mitigate the effects of transition curvature and 2-D ISI for both LT and HT of HIMR. First, a designed writer with splitting main poles produces the spatially nonuniform write field along the crosstrack direction to correct the transition curvature of LT. Then the multitrack detection with JLNN and improved Bahl–Cocke–Jelinek–Raviv (BCJR) detector (JLNN-IB) algorithm is studied to further mitigate the effects of residual transition curvatures, thermal jitters, and 2-D ISI for both HT and LT. Specifically, the readback signals of read head array and decoded log-likelihood ratio (LLR) outputted by the low-density parity check (LDPC) decoder are fed into JLNN to obtain the equalized signal and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$a$ </tex-math></inline-formula> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">priori</i> probability (AP) of three tracks. Then the equalized signal as well as AP of current track and corresponding soft bit estimations of adjacent tracks are embedded into the branch metrics of improved BCJR detector for data detection, and the LDPC decoder is cascaded for the error correction. The simulation indicates that at the recording density of 2.11 Tb/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the proposed comprehensive writer design and JLNN-IB algorithm provide 9.2 and 9.7 dB signal to noise ratio (SNR) gains compared to the conventional 2-D neural network equalizer and 2-D linear equalizer under the uniform write field and circular thermal profile, respectively.

Turbo-Detection for Multilayer Magnetic Recording Using Deep Neural Network-Based Equalizer and Media Noise Predictor

This article considers deep neural network (DNN)-based turbo-detection for multilayer magnetic recording (MLMR), an emerging hard disk drive (HDD) technology that uses vertically stacked magnetic media layers with readers above the top-most layer. The proposed system uses two layers with two upper layer tracks and one lower layer track. The reader signals are processed by convolutional neural networks (CNNs) to separate the upper and lower layer signals and equalize them to 2-D and 1-D partial response (PR) targets, respectively. The upper and lower layer signals feed 2-D and 1-D Bahl–Cocke–Jelinek–Raviv (BCJR) detectors, respectively. The detectors’ soft outputs feed a multilayer CNN-based media noise predictor whose predicted noise outputs are fed back to the BCJR equalizers to reduce their bit error rates (BERs). The BCJR equalizers also interface with low-density parity-check (LDPC) decoders. Additional BER reductions are achieved by sending soft-information from the upper layer BCJR to the lower layer BCJR. Simulations of this turbo-detection system on a two-layer MLMR signal generated by a grain-switching-probabilistic (GSP) media model show density gains of 11.32% over a comparable system with no lower layer and achieve an overall density of 2.6551 terabits per square inch (Tb/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ).

Improving LDPC and turbo LDPC codes using Collection of Punctured Codes Decoding (CPCD)

In our previous paper [1], a novel CPCD technique has been introduced to significantly improve decoding of LDPC codes over the known sum product algorithm (SPA) decoding. However, results presented in [1] were limited to shorter low density parity check (LDPC) codes and transmission over an addition white Gaussian noise (AWGN) channels using QPSK modulation. In this study, we demonstrate that CPCD can achieve significant gains regardless of the length of the code or the modulation technique used for transmission or the type of the channel including fading channels. In addition, a novel turbo-CPCD technique that follows the principle of turbo LDPC is introduced. It is shown here that CPCD and turbo-CPCD can perform about 0.2−1.5 dB better than SPA decoding and turbo LDPC codes.

A Polygonal Line Min-Sum Decoding Scheme for Low Density Parity Check Codes

Low-density parity-check (LDPC) codes are widely used as error correction codes in new generation digital TV standards, such as the second generation of terrestrial digital video broadcasting standard (DVB-T2), Advanced Television Systems Committee (ATSC) 3.0, etc. The nonlinear belief propagation (BP) algorithm has excellent decoding performance for LDPC codes, but is often simplified in hardware implementations by linear min-sum (MS) algorithm due to its high complexity. This simplification also leads to over-estimation problems, which can be corrected by adding factors in conventional algorithms (e.g., normalized min-sum (NMS), offset min-sum (OMS), and variable scaling normalized min-sum (VMS) algorithms). However, the correction factors of these modified MS algorithms cannot adapt to different channels and modulations, and the performance needs further improvement. In this paper, the concepts of over-estimation value (OEV) and over-estimation rate (OER) are introduced to describe the over-estimation problem of the MS algorithm. Then, under the guidance of OEV and OER, a polygonal line min-sum (PMS) algorithm with correction factors adapted to different channels and modulations is proposed according to LLR distribution. Following the properties of OEV and OER, PMS algorithm is further simplified into Simplified PMS (SPMS) algorithm. LDPC codes from ATSC 3.0 are adopted in this paper to evaluate SPMS algorithm in comparison with the conventional algorithms. Extensive simulation results show that the SPMS algorithm for ATSC 3.0 LDPC decoder has at most 1.61dB, 0.24dB and 0.36dB gain over NMS, OMS and VMS algorithms respectively when frame error rate (FER) is at 10⁻⁴ level over additive white Gaussian noise (AWGN) channel with QPSK modulation. More importantly, the simulation results show that the SPMS algorithm can achieve much better performance than these modified MS algorithms over AWGN and Rayleigh channel with higher-order modulations or under limited maximum iteration number.

Efficient First Four Minimum Values Finder for NB-LDPC Decoders With Compressed Messages

Trellis min-max algorithm based nonbinary low-density parity-check (NB-LDPC) decoders with compressed messages offer promising performance compared with their conventional counterparts. Recent studies have shown that reducing check-node output information to a set of four most reliable intrinsic messages strikes a balance between the hardware complexity and error-correcting performance of the decoder. Therefore, an efficient architecture to find the first four minimum values (F4M) from a given set of values is greatly required. This brief proposes an algorithm to derive F4M from two four-sorted sequences, with subsequent efficient tree structure based architecture to construct the F4M finder. To demonstrate the hardware efficiency, the proposed F4M finder architecture implementations using TSMC 90-nm CMOS technology were conducted. Experimental results confirmed that the latency of the proposed F4M finder was approximately halved compared with that of design in the state-of-the-art work. In particular, the proposed F4M finder architecture can be adopted to further improve the performance of the NB-LDPC decoders.

Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing

A practical min-sum algorithm is associated with tree-based comparison units for the check-node operation, being a major bottleneck in designing low-cost and energy-efficient low-density parity-check (LDPC) decoders. In this brief, we present a cost-effective LDPC decoder architecture by changing its internal computing resolution for the power-hungry check-node processing. The proposed mixed-resolution comparison offers significant advantages in terms of both area and energy, while achieving error-correcting performance within 0.3 dB of the previous normalized min-sum (NMS) algorithm for a (1644, 1408) quasi-cyclic LDPC code of the 5G New Radio specifications. Compared to the baseline NMS architecture, the proposed decoder in a 65-nm CMOS technology reduces the hardware complexity and the power consumption by 28.4% and 23.1%, respectively, enhancing the area efficiency by more than 88.2%.

Advanced ISDB-T and ATSC 3.0 LDPC Codes Performance and Complexity Comparison

This paper presents a comparative performance and complexity analysis of the advanced ISDB-T and ATSC 3.0 Low-Density Parity-Check (LDPC) codes using the Sum-Product Algorithm and Min-Sum Algorithm LDPC decoders. The performance value for each of the code rates of the LDPC codes over an additive white Gaussian noise (AWGN) channel and Rayleigh fading channel is presented. The mathematical representation of each of the SPA and MSA decoders is presented along with the calculated and measured numerical complexity values.

Reconfigurable Low-Density Parity-Check (LDPC) Decoder for Multi-Standard 60 GHz Wireless Local Area Networks

In this study, a reconfigurable low-density parity-check (LDPC) decoder is designed with good hardware sharing for IEEE 802.15.3c, 802.11ad, and 802.11ay standards. This architecture flexibly supports 12 types of parity-check matrix. The switching network adopts an architecture that can flexibly switch between different inputs and achieves a low hardware complexity. The check node unit adopts a switchable 8/16/32 reconfigurable structure to match different row weights at different code rates and uses the normalised probability min-sum algorithm to simplify the structure of searching for the minimum value. Finally, the chip is implemented using the TSMC 40 nm CMOS process, based on the IEEE 802.11ad standard decoder, extended to support the IEEE 802.15.3c standard, and upwardly compatible with the next-generation advanced standard IEEE 802.11ay. The chip core size was 1.312 mm × 1.312 mm, the operating frequency was 117 MHz when the maximum number of iterations was five with the power consumption of 57.1 mW, and the throughput of 5.24 Gbps and 3.90 Gbsp was in the IEEE 802.11ad and 802.5.3c standards, respectively.

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders.

This paper presents a low-complexity multi-size circular-shift network (MCSN) structure for 5th-generation (5G) New Radio (NR) quasi-cyclic low-density parity-check (QC-LDPC) decoders. In particular, a fine-coarse approach-based multi-size cyclic shift network, which decomposes the cyclic shift size into fine part and coarse part, is introduced. The proposed MCSN structure is composed of a pre-rotator performing the fine part of the cyclic shift, and a main rotator executing the coarse part of the cyclic shift. In addition, a forward routing circular-shift (FRCS) network, which is based on the barrel shifter and the forward routing process is presented. The proposed switch network is able to support all 51 different submatrix sizes as defined in the 5G NR standard through an efficient forward routing switch network and help reduce the hardware complexity using a cyclic shift size decomposition method. The proposed MCSN is analyzed, and indicates a substantial reduction in the hardware complexity. The experimental results on TSMC 65-nm CMOS technology show that the proposed MCSN structure for 5G NR LDPC decoder offers an area saving up to 56.75% compared to related works in the literature.

Neural Network Aided Impulsive Perturbation Decoding for Short Raptor-Like LDPC Codes

As short packet communications become more important, multi-round belief propagation decoding with impulsive perturbation (MBPD-IP) was proposed to improve the decoding of short low-density parity-check (LDPC) codes. To operate the MBPD-IP effectively, it is crucial to select proper symbols to be perturbed in as few trials as possible. Unfortunately, existing perturbation symbol selection criteria are heuristic and not effective for special codes such as raptor-like (RL) LDPC codes. In this letter, a neural network (NN) based perturbation symbol selection scheme for MBPD-IP is proposed where the symbols to be perturbed are selected from a pre-trained NN. It is shown that the proposed scheme performs significantly better than existing schemes for the RL LDPC code of 5G new radio and still works well for plain code structures.

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders.

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder's potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

High-Throughput Multi-Frame Decoding of QC-LDPC Codes With Modified Rejection-Based Minimum Finding

The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which is able to find the one-hot sequence of the minimum location instead of its index. We show that this modification effectively reduces the complexity of min-sum decoding algorithm. Additionally, we reveal a pipelining potential in such a rejection-based architecture which facilitates the multi-frame decoding of Low-Density Parity-Check (LDPC) codes and therefore results in an improvement in decoding throughput with bearable hardware overhead. Synthesis and floorplanning in an industrial 28 nm CMOS technology show improved results in terms of throughput, power, and chip area.

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.

Reliability‐based quantization for soft decoding of LDPC codes in short‐reach optical links

Efficient quantizer design is vital in high-speed optical receivers. In this paper, the authors propose a three-level (1.5-bit) reliability-based quantizer for low-complexity soft decoding of low-density parity-check (LDPC) codes, and show that it outperforms a conventional quantizer employing eight levels (3 bits). Different approaches for obtaining the quantization thresholds are discussed, and it is shown that the achievable channel capacity with the proposed quantizer is within 0.4 dB of the Shannon limit of the unquantized channel. Rate-compatible LDPC codes are also designed tailored to the asymmetric optical channel terminated with the proposed reliability-based quantizer, and it is shown that the resulting quantizer-aware LDPC codes significantly outperform other existing codes of similar rates.

Efficient Iterative Timing Recovery of Low-Density Parity-Check Decoding Metrics Using the Steepest Descent Algorithm for Satellite Communications at Low SNRs

An efficient iterative timing recovery via steepest descent of low-density parity-check (LDPC) decoding metrics is presented. In the proposed algorithm, a more accurate symbol timing synchronization is achieved at a low signal-to-noise (SNR) without any pilot symbol by maximizing the sum of the square of all soft metrics in LDPC decoding. The principle of the above-proposed algorithm is analyzed theoretically with the evolution trend of the probability mean of the soft LDPC decoding metrics by the Gaussian approximation. In addition, an efficiently approximate gradient descent algorithm is adopted to obtain excellent timing recovery with rather low complexity and global convergence. Finally, a complete timing recovery is accomplished where the proposed scheme performs fine timing capture, followed by a traditional Mueller–Müller (M&amp;M) timing recovery, which acquires timing track. Using the proposed iterative timing recovery method, the simulation results indicate that the performance of the LDPC coded binary phase shift keying (BPSK) scheme with rather large timing errors is just within 0.1 dB of the ideal code performance at the cost of some rational computation and storage. Therefore, the proposed iterative timing recovery can be efficiently applied on occasions of the weak signal timing synchronization in satellite communications and so on.

Enhancing Performance of Lossy Compression on Encrypted Gray Images through Heuristic Optimization of Bitplane Allocation

Nowadays, it remains a major challenge to efficiently compress encrypted images. In this paper, we propose a novel encryption-then-compression (ETC) scheme to enhance the performance of lossy compression on encrypted gray images through heuristic optimization of bitplane allocation. Specifically, in compressing an encrypted image, we take a bitplane as a basic compression unit and formulate the lossy compression task as an optimization problem that maximizes the peak signal-to-noise ratio (PSNR) subject to a given compression ratio. We then develop a heuristic strategy of bitplane allocation to approximately solve this optimization problem, which leverages the asymmetric characteristics of different bitplanes. In particular, an encrypted image is divided into four sub-images. Among them, one sub-image is reserved, while the most significant bitplanes (MSBs) of the other sub-images are selected successively, and so are the second, third, etc., MSBs until a given compression ratio is met. As there exist clear statistical correlations within a bitplane and between adjacent bitplanes, where bitplane denotes those belonging to the first three MSBs, we further use the low-density parity-check (LDPC) code to compress these bitplanes according to the ETC framework. In reconstructing the original image, we first deploy the joint LDPC decoding, decryption, and Markov random field (MRF) exploitation to recover the chosen bitplanes belonging to the first three MSBs in a lossless way, and then apply content-adaptive interpolation to further obtain missing bitplanes and thus discarded pixels, which is symmetric to the encrypted image compression process. Experimental simulation results show that the proposed scheme achieves desirable visual quality of reconstructed images and remarkably outperforms the state-of-the-art ETC methods, which indicates the feasibility and effectiveness of the proposed scheme.