Efficient First Four Minimum Values Finder for NB-LDPC Decoders With Compressed Messages

Abstract

Trellis min-max algorithm based nonbinary low-density parity-check (NB-LDPC) decoders with compressed messages offer promising performance compared with their conventional counterparts. Recent studies have shown that reducing check-node output information to a set of four most reliable intrinsic messages strikes a balance between the hardware complexity and error-correcting performance of the decoder. Therefore, an efficient architecture to find the first four minimum values (F4M) from a given set of values is greatly required. This brief proposes an algorithm to derive F4M from two four-sorted sequences, with subsequent efficient tree structure based architecture to construct the F4M finder. To demonstrate the hardware efficiency, the proposed F4M finder architecture implementations using TSMC 90-nm CMOS technology were conducted. Experimental results confirmed that the latency of the proposed F4M finder was approximately halved compared with that of design in the state-of-the-art work. In particular, the proposed F4M finder architecture can be adopted to further improve the performance of the NB-LDPC decoders.