Low-cost Field Programmable Gate Array Research Articles

Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial Reconfiguration

With applications to become increasingly compute- and data-intensive, requiring more processing power, many Internet of Things (IoT) platforms in robots, drones, and autonomous vehicles that implement neural network inference, cryptographic functions or signal processing (e.g., multimedia, communication), employ field programmable gate arrays (FPGAs). At the same time, dynamic partial reconfiguration (DPR) in modern FPGAs enable changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. This is especially useful to update functions of IoT devices while in operation for bug fixing or functionality adjustments and, more importantly, when these IoT devices integrate low-cost FPGAs that can hardly realize many hard accelerators. To deal with one of the major limitations of using partial reconfiguration in IoT devices, this work introduces techniques to flexibly use DPR, namely, FLEXDPR, by sharing reconfigurable partitions among different accelerator functions and by supporting virtual relocation of these functions. Experimental results on the Xilinx Zynq-7000 platform reveal energy and latency efficiency improvements of about 20%, on average. Overall, the suggested approach can reduce partial reconfiguration overhead while easing the scheduler’s decisions for the deployment of hardware functions throughout time and space in a performance-conscious manner.

Developing a Portable Fluorescence Imaging Device for Fish Freshness Detection.

Rapid detection of fish freshness is of vital importance to ensuring the safety of aquatic product consumption. Currently, the widely used optical detecting methods of fish freshness are faced with multiple challenges, including low detecting efficiency, high cost, large size and low integration of detecting equipment. This research aims to address these issues by developing a low-cost portable fluorescence imaging device for rapid fish freshness detection. The developed device employs ultraviolet-light-emitting diode (UV-LED) lamp beads (365 nm, 10 W) as excitation light sources, and a low-cost field programmable gate array (FPGA) board (model: ZYNQ XC7Z020) as the master control unit. The fluorescence images captured by a complementary metal oxide semiconductor (CMOS) camera are processed by the YOLOv4-Tiny model embedded in FPGA to obtain the ultimate results of fish freshness. The circuit for the YOLOv4-Tiny model is optimized to make full use of FPGA resources and to increase computing efficiency. The performance of the device is evaluated by using grass carp fillets as the research object. The average accuracy of freshness detection reaches up to 97.10%. Moreover, the detection time of below 1 s per sample and the overall power consumption of 47.1 W (including 42.4 W light source power consumption) indicate that the device has good real-time performance and low power consumption. The research provides a potential tool for fish freshness evaluation in a low-cost and rapid manner.

Efficient and Accurate Analog Voltage Measurement Using a Direct Sensor-to-Digital Port Interface for Microcontrollers and Field-Programmable Gate Arrays

Portable sensor systems are usually based on microcontrollers and/or Field-Programmable Gate Arrays (FPGAs) that are interfaced with sensors by means of an Analog-to-Digital converter (ADC), either integrated in the computing device or external. An alternative solution is based on the direct connection of the sensors to the digital input port of the microcontroller or FPGA. This solution is particularly interesting in the case of devices not integrating an internal ADC or featuring a small number of ADC channels. In this paper, a technique is presented to directly interface sensors with analog voltage output to the digital input port of a microcontroller or FPGA. The proposed method requires only a few passive components and is based on the measurements of the duty cycle of a digital square-wave signal. This technique was investigated by means of circuit simulations using LTSpice and was implemented in a commercial low-cost FPGA device (Gowin GW1NR-9). The duty cycle of the square-wave signal features a good linear correlation with the analog voltage to be measured. Thus, a look-up table to map the analog voltage values to the measured duty cycle is not required with benefits in terms of memory occupation. The experimental results on the FPGA device have shown that the analog voltage can be measured with a maximum accuracy of 1.09 mV and a sampling rate of 9.75 Hz. The sampling rate can be increased to 31.35 Hz and 128.31 Hz with an accuracy of 1.61 mV and 2.68 mV, respectively.

A Heterogeneous Inference Framework for a Deep Neural Network

Artificial intelligence (AI) is one of the most promising technologies based on machine learning algorithms. In this paper, we propose a workflow for the implementation of deep neural networks. This workflow attempts to combine the flexibility of high-level compilers (HLS)-based networks with the architectural control features of hardware description languages (HDL)-based flows. The architecture consists of a convolutional neural network, SqueezeNet v1.1, and a hard processor system (HPS) that coexists with acceleration hardware to be designed. This methodology allows us to compare solutions based solely on software (PyTorch 1.13.1) and propose heterogeneous inference solutions, taking advantage of the best options within the software and hardware flow. The proposed workflow is implemented on a low-cost field programmable gate array system-on-chip (FPGA SOC) platform, specifically the DE10-Nano development board. We have provided systolic architectural solutions written in OpenCL that are highly flexible and easily tunable to take full advantage of the resources of programmable devices and achieve superior energy efficiencies working with a 32-bit floating point. From a verification point of view, the proposed method is effective, since the reference models in all tests, both for the individual layers and the complete network, have been readily available using packages well known in the development, training, and inference of deep networks.

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method.

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity.

An FPGA-Based Reconfigurable FIR Filter for SDR Applications

This article presents a proposal of a reconfigurable FIR filter capable of covering the most common wireless communication standards on software-defined radio applications. The filter was implemented using a low-cost field programmable gate array, Cyclone IV EP4CE22F17C6 model from Altera®. System design is presented together with simulation results. Validation is done for a 500 kHz base-band noisy signal. The synthesized design uses 5,259 logic elements of which 4,778 were used for combinational logic blocks and 513 for dedicated logic registers, which represents 22% of total used FPGA capacity. The maximum sampling frequency supported by the architecture is 23.24 MHz.

Enabling Time-Synchronized Hybrid Networks With Low-Cost IoT Modules

Precisely synchronized communication is a major precondition for many industrial applications. At the same time, hardware cost and power consumption need to be kept as low as possible in the Internet-of-Things (IoT) paradigm. While many wired solutions on the market achieve these requirements, wireless alternatives are an interesting field for research and development. This paper presents a novel IEEE802.11n/ac wireless solution, exhibiting several advantages over state-of-the-art competitors. It is based on a market-available wireless System on a Chip with modified low-level communication firmware combined with a low-cost field-programmable gate array. By achieving sub-microsecond synchronization accuracy, our solution outperforms the precision of low-cost products by almost four orders of magnitude. Based on inexpensive hardware, the presented wireless module is up to 20 times cheaper than Software-Defined-Radio solutions with comparable timing accuracy. Moreover, it consumes three to five times less power. To back up our claims, we report data that we collected with a high sampling rate (2000 samples per second) during an extended measurement campaign of more than 120 hours, which makes our experimental results far more representative than others reported in the literature. Additional support is provided by the size of the testbed we used during the experiments, composed of a hybrid network with nine nodes divided into two independent wireless segments connected by a wired backbone. In conclusion, we believe that our novel Industrial IoT module architecture will have a significant impact on the future technological development of high-precision time-synchronized communication for the cost-sensitive industrial IoT market.

FPGA implementation of two multilayer perceptron neural network in cascade for efficient real time hand gestures tracking

This paper presents implementation of a hand gestures tracking system with a fully connected multilayer perceptron and a supervised sequential learning algorithm on low cost FPGAs (Field Programmable Gate Array). Two networks are used in the study. The first network is trained to detect skins and the second identifies face and hand gestures. Also, a binary image is made from the first network, which is fed into the second network as input. Skin network has two output classes, and hand network 6. The first network recognizes skin and non-skin images and the other distinguishes hands from faces while hand gestures are tracked and classified. Both networks are trained in Matlab before each was implemented on a separate FPGA and the two FPGAs are then connected to each other. Finally, the overall result is compared. Both networks are implemented on Xilinx Spartan XC3S1000 4fg456. Two hardware-implemented networks are applied to a video sequence frame by frame. Features of both hands are extracted and the network is trained using a constructed vector to track left and right hands. Results show that the implemented system enjoys a suitable trade-off between accuracy and speed, reaching 208 fps with the least memory usage. This method has been compared to other methods, as well as methods in which only one threshold is used to detect skin color.

Generalized Model Predictive Pulse Pattern Control Based on Small-Signal Modeling—Part 2: Implementation and Analysis

A newly proposed model predictive pulse pattern controller, which is applicable to higher-order converter systems, is implemented on a low-cost field-programmable gate array. It is shown that how the computations of the underlying quadratic program of the control algorithm can be reduce, thus enabling a resource-efficient implementation. The implemented control algorithm is evaluated via hardware-in-the-loop simulations. The results show that the proposed controller achieves a short settling time during transients and the superior harmonic performance of optimized pulse patterns during steady-state operation.

A 4.8ps root-mean-square resolution time-to-digital converter implemented in a 20nm Cyclone-10 GX field-programmable gate array.

It is difficult to improve the resolution and precision of a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) in time interval measurement. In this study, we design a carry-look-ahead delay chain structure and integrate an interleaved sampling method with an online calibration and bin readjustment approach to implement a TDC. We take advantage of the adaptive logic module units applied in a Cyclone-10 GX (10CX220YF780E5G), which is a 20nm low-power consumption and low-cost FPGA. In this new generation FPGA, we implemented a high-precision time interval measurement, which exceeded all our previous works with a 4.8ps root-mean-square resolution and a 5.68ps least-significant-bit resolution.

A neural network-based algorithm for simultaneous event positioning and timestamping in monolithic scintillators

Objective. Monolithic scintillator crystals coupled to silicon photomultiplier (SiPM) arrays are promising detectors for PET applications, offering spatial resolution around 1 mm and depth-of-interaction information. However, their timing resolution has always been inferior to that of pixellated crystals, while the best results on spatial resolution have been obtained with algorithms that cannot operate in real-time in a PET detector. In this study, we explore the capabilities of monolithic crystals with respect to spatial and timing resolution, presenting new algorithms that overcome the mentioned problems. Approach. Our algorithms were tested first using a simulation framework, then on experimentally acquired data. We tested an event timestamping algorithm based on neural networks which was then integrated into a second neural network for simultaneous estimation of the event position and timestamp. Both algorithms are implemented in a low-cost field-programmable gate array that can be integrated in the detector and can process more than 1 million events per second in real-time. Results. Testing the neural network for the simultaneous estimation of the event position and timestamp on experimental data we obtain 0.78 2D FWHM on the (x, y) plane, 1.2 depth-of-interaction FWHM and 156 coincidence time resolution on a LYSO monolith read-out by 64 Hamamatsu SiPMs. Significance. Our results show that monolithic crystals combined with artificial intelligence can rival pixellated crystals performance for time-of-flight PET applications, while having better spatial resolution and DOI resolution. Thanks to the use of very light neural networks, event characterization can be done on-line directly in the detector, solving the issues of scalability and computational complexity that up to now were preventing the use of monolithic crystals in clinical PET scanners.

An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks

Upper-Extremity motor impairment affects millions of Americans due to cerebrovascular incidents, spinal cord injuries, or brain trauma. Current therapy practices used to assist these individuals in regaining motor functionality often require extensive time at rehabilitation facilities with potentially prohibitive travel or financial costs. This work presents a mobile low-cost field programmable gate array (FPGA)-smart rehabilitation system that can be used in home environments. The prototype is a rehabilitation table instrumented with a capacitive sensor array (CSA) to track upper-extremity motions of the user through proximity or touch. In addition, inertial measurement units (IMUs) are placed on the affected upper limb and combined with the CSA data with our sensor fusion signal processing architecture. Motions are classified and evaluated using multi-task convolutional recurrent neural networks with three additional motion quality output classes to personalize recognition based on the particular motor skills of each patient. The prototype achieves above 99% accuracy with 32-bit fixed-point format implementation for recognizing dynamic motions and identifying unnatural characteristics (i.e., tremor or limited flexion and extension) in upper limb motions based on sensor values. The convolutional recurrent neural network (C-RNN) fusion classification network is implemented on a 200 MHz Zynq ZCU104 FPGA using an HLS-based design optimized with pipelining and parallelism techniques and achieves 5.4x speedup compared to ARM® Cortex-A53 implementation running at an operating frequency of 1.3 GHz. The prototype is also demonstrated to perform the machine learning classification in real-time.

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA.

FPGA-Based High-Speed Optical Fiber Sensor Based on Multitone-Mixing Interferometry

We report a real-time high-speed fiber Bragg grating (FBG) interrogator based on a fiber-optic interferometer. The signal processing is performed by using a low-cost field-programmable gate array (FPGA) system, which is programed to implement a phase-generated carrier (PGC) demodulation algorithm with multitone mixing (MTM) to provide distortion-free signals with high tolerance to modulation depth variations and light intensity fluctuations. The system can stream data at rates up to 1 MS/s and allows multiplexed processing up to two channels. Experimental results show simultaneous measurements of two FBGs, one of which was actuated at frequencies up to 100 kHz. The system features a 3-dB bandwidth of 280 kHz, and a dynamic wavelength resolution of 4.7 fm/Hz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\mathrm {1/2}}$ </tex-math></inline-formula> . We also demonstrate a strong reduction of distortion using the MTM approach with respect to the standard technique. Finally, we study the origin of the noise, demonstrating a reduction in common noise sources by using one of the FBGs as a reference. The system can measure FBGs centered at any position within the spectral band of the source, is polarization-independent, and is easily scalable to more than two measurement channels from the same interferometer.

Multi-Channel FPGA Time-to-Digital Converter With 10 ps Bin and 40 ps FWHM

We present a novel architecture for multi-channel time-to-digital converters (TDCs) to be implemented into low-cost field-programmable gate arrays (FPGAs), achieving 10-ps least significant bit (LSB), 164- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> full-scale range, and good linearity both in terms of differential nonlinearity (DNL) and integral nonlinearity (INL). The conceived architecture is based on the carry chain delay line model and wave union A method: the positions of both rising and falling edges that propagate in multiple parallel carry chains are recorded each time there is an HIT input. This technique effectively subdivides the ultrawide bins improving the measurement precision and, combined with the sliding-scale technique and continuous code density calibration, improves the TDC linearity. Employing the proposed architecture, we have implemented in a Xilinx Artix-7 FPGA a TDC with 20 timestamp units and validated the device in a time-correlated single photon counting (TCSPC) setup, when connected to an array chip with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times 5$ </tex-math></inline-formula> single-photon avalanche diodes (SPADs).

MLoF: Machine Learning Accelerators for the Low-Cost FPGA Platforms

In Internet of Things (IoT) scenarios, it is challenging to deploy Machine Learning (ML) algorithms on low-cost Field Programmable Gate Arrays (FPGAs) in a real-time, cost-efficient, and high-performance way. This paper introduces Machine Learning on FPGA (MLoF), a series of ML IP cores implemented on the low-cost FPGA platforms, aiming at helping more IoT developers to achieve comprehensive performance in various tasks. With Verilog, we deploy and accelerate Artificial Neural Networks (ANNs), Decision Trees (DTs), K-Nearest Neighbors (k-NNs), and Support Vector Machines (SVMs) on 10 different FPGA development boards from seven producers. Additionally, we analyze and evaluate our design with six datasets, and compare the best-performing FPGAs with traditional SoC-based systems including NVIDIA Jetson Nano, Raspberry Pi 3B+, and STM32L476 Nucle. The results show that Lattice’s ICE40UP5 achieves the best overall performance with low power consumption, on which MLoF averagely reduces power by 891% and increases performance by 9 times. Moreover, its cost, power, Latency Production (CPLP) outperforms SoC-based systems by 25 times, which demonstrates the significance of MLoF in endpoint deployment of ML algorithms. Furthermore, we make all of the code open-source in order to promote future research.

Configurable Hardware Core for IoT Object Detection

Object detection is an important task for many applications, like transportation, security, and medical applications. Many of these applications are needed on edge devices to make local decisions. Therefore, it is necessary to provide low-cost, fast solutions for object detection. This work proposes a configurable hardware core on a field-programmable gate array (FPGA) for object detection. The configurability of the core allows its deployment on target devices with diverse hardware resources. The object detection accelerator is based on YOLO, for its good accuracy at moderate computational complexity. The solution was applied to the design of a core to accelerate the Tiny-YOLOv3, based on a CNN developed for constrained environments. However, it can be applied to other YOLO versions. The core was integrated into a full system-on-chip solution and tested with the COCO dataset. It achieved a performance from 7 to 14 FPS in a low-cost ZYNQ7020 FPGA, depending on the quantization, with an accuracy reduction from 2.1 to 1.4 points of mAP50.

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

Hardware-in-the-loop (HIL) simulations of power converters must achieve a truthful representation in real time with simulation steps on the order of microseconds or tens of nanoseconds. The numerical solution for the differential equations that model the state of the converter can be calculated using the fourth-order Runge–Kutta method, which is notably more accurate than Euler methods. However, when the mathematical error due to the solver is drastically reduced, other sources of error arise. In the case of converters that use deadtimes to control the switches, such as any power converter including half-bridge modules, the inductor current reaching zero during deadtimes generates a model error large enough to offset the advantages of the Runge–Kutta method. A specific model is needed for such events. In this paper, an approximation is proposed, where the time step is divided into two semi-steps. This serves to recover the accuracy of the calculations at the expense of needing a division operation. A fixed-point implementation in VHDL is proposed, reusing a block along several calculation cycles to compute the needed parameters for the Runge–Kutta method. The implementation in a low-cost field-programmable gate arrays (FPGA) (Xilinx Artix-7) achieves an integration time of 1μs. The calculation errors are six orders of magnitude smaller for both capacitor voltage and inductor current for the worst case, the one where the current reaches zero during the deadtimes in 78% of the simulated cycles. The accuracy achieved with the proposed fixed point implementation is very close to that of 64-bit floating point and can operate in real time with a resolution of 1μs. Therefore, the results show that this approach is suitable for modeling converters based on half-bridge modules by using FPGAs. This solution is intended for easy integration into any HIL system, including commercial HIL systems, showing that its application even with relatively high integration steps (1μs) surpasses the results of techniques with even faster integration steps that do not take these events into account.

Efficient Pipelined Circuits for Histogram-based Tone Mapping of Nonlinear CMOS Image Sensors

Abstract Tone mapping is extensively researched to address the issue of displaying high dynamic range (DR) scenes on low DR displays. Even though several tone-mapping operators (TMOs) exist, not all are designed for hard real time. The operator has to be capable of scaling up the spatial resolution without compromising the frame rate. The implementation of a TMO should also be simple enough to embed in low-cost platforms for imaging systems. A computationally efficient, and well accepted, class of TMOs are global ones based on histograms. This work presents a method to implement TMOs that use histograms. This method is suitable for low-cost field-programmable gate arrays (FPGAs), using simple components such as adders, multipliers, and random access memories, and is particularly suited for a nonlinear CMOS image sensor (CIS) operating continuously in hard real time. The authors develop a fixed-point design, validated in bit-true fashion using Xilinx and Altera tools, from a background algorithm implemented using Matlab. Our generic design uses pipelined circuits and operates with low latency. The use of a hardware description language to model our circuits guarantees portability and modularity. Moreover, the complete TMO is generated from design parameters and a design template. The architecture is robust and scales well from kilopixel to megapixel formats. The circuits achieve 30 frames per second, at high definition resolutions, while occupying only a small fraction of the available logic elements in a low-cost FPGA device.

A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection

The echo state network (ESN) is a recently developed machine-learning paradigm whose processing capabilities rely on the dynamical behavior of recurrent neural networks. Its performance outperforms traditional recurrent neural networks in nonlinear system identification and temporal information processing applications. We design and implement a cost-efficient ESN architecture on field-programmable gate array (FPGA) that explores the full capacity of digital signal processor blocks on low-cost and low-power FPGA hardware. Specifically, our scalable ESN architecture on FPGA exploits Xilinx DSP48E1 units to cut down the need of configurable logic blocks. The proposed architecture includes a linear combination processor with negligible deployment of configurable logic blocks and a high-accuracy nonlinear function approximator. Our work is verified with the prediction task on the classical NARMA dataset and a symbol detection task for orthogonal frequency division multiplexing systems using a wireless communication testbed built on a software-defined radio platform. Experiments and performance measurement show that the new ESN architecture is capable of processing real-world data efficiently for low-cost and low-power applications.