Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

Juan David Espitia Espitia Castillo,Enrique Cantó Navarro,Enric Vidal-Idiarte

doi:10.3390/electronics11030447

Juan David Espitia Espitia Castillo, Enrique Cantó Navarro + Show 1 more

Open Access

https://doi.org/10.3390/electronics11030447

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Journal: Electronics	Publication Date: Feb 2, 2022
Citations: 2	License type: CC BY 4.0

Affiliation: Rovira i Virgili University

Abstract

The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA.

Highlights

In the field of control systems, a set of signals are collected from sensors in order to perform the necessary actions to obtain the desired output from a reference indicated by the user [1,2]
A possible solution is to avoid the need for analog-to-digital converters (ADC) as shown in [7], where a digital signal is connected to a field programmable gate array (FPGA) pin and its temporal width is measured by internal counters
FPGAs allow the implementation of ADCs, which, in the simplest case, requires a pin connected to a passive resistance-capacity (RC) filter and another pin to an internal logic gate acting as a analog comparator when the threshold voltage is exceed

Summary

Introduction

In the field of control systems, a set of signals are collected from sensors in order to perform the necessary actions to obtain the desired output from a reference indicated by the user [1,2]. Using discrete ADCs, such as LTC1406 (8-bit ADC 200 MSPS), in applications that require a high number of ADCs can inhibit its connection due the limited quantity of I/O pins in low-cost devices. In this case, a possible solution is to avoid the need for ADCs as shown in [7], where a digital signal is connected to a FPGA pin and its temporal width is measured by internal counters. The implementation of ADCs on FPGAs presents limitations, such as external analog circuits (integrators or filters), performance that cannot achieve discrete ADCs, and higher power consumption due to programmable technology

Results

Discussion

Conclusion