A time-based successive approximation register analog-to-digital converter using a pulse width modulation technique with a single capacitor

Abstract

A time-based successive approximation register (SAR) analog to digital converter (ADC) using a pulse width modulation is presented for scaled CMOS technologies. A binary search in the proposed ADC performs on time-domain signal processing using a pulse width modulation with a single capacitor. Since the ADC employs time-domain signal processing, the proposed ADC does not suffer from a process variation such as a capacitor mismatch. The proposed ADC also has low input capacitance, since it has the single capacitor, not the capacitor array in conventional SAR ADC. A feasibility of the proposed ADC is verified by simulations using ADC models having 10 bit resolution in ideal condition as well as in non-ideal condition.