Abstract
The efficiency in terms of accuracy, power consumption, and on-chip area of Successive Approximation Register (SAR) Analog to Digital Converter (ADC) depends on the charge-redistribution Digital to Analog Converter (DAC). Thus, the optimal design of SAR ADC demands accurate design and analysis of the DAC unit. In this work, a MATLAB model of charge-redistribution DAC based on Binary Weighted with attenuation capacitor array has been presented for the design of a SAR ADC. This MATLAB based model performs statistical as well as parametric simulations including the effects of parasitic capacitances and capacitor mismatch which help in the accurate estimation of static and dynamic non-linearity of the DAC unit.
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