A design of 8 bit SAR ADC using monotonie capacitive switching procedure in 90nm

Abstract

Successive approximation register (SAR) analog to digital converters (ADC) are extensively used for low speed and low power applications. This paper presents a design of an 8 bit SAR ADC which uses monotonic capacitor switching technique. This switching technique reduces the total capacitance in the DAC circuit which indirectly leads to reduced power consumption. Dynamic latch comparator is used among the key building blocks of SAR ADC, the usage of this comparator reduces the leakage current in the circuit. The proposed 8 bit SAR ADC is implemented by using 90nm CMOS technology and works at supply voltage of 1.2V. The designed SAR analog to digital converter consumes 69.85μW power.