Low Capacitive Load Research Articles

Virtualized and fault-tolerant inter-layer-links for 3D-ICs

Through Silicon Via (TSV) is the state-of-the-art vertical interconnect technology in three dimensional Integrated Circuits (3D-ICs). TSVs offer short wire length with low capacitive load and, hence, fast connections between two or more chip layers. On the other hand, TSVs consume a relative large amount of chip area and are error prone during manufacturing resulting in a dramatic yield drop for large TSV counts. Because of their short wire length, TSVs can be clocked much higher than conventional intra-layer links. To efficiently utilize the vertical bandwidth of TSVs, this paper proposes multiplexing several virtual links with dynamically allocated bit rates for guaranteed service connections via a shared TSV-Hub-Array. Virtual links can be state-of-the-art interconnects like busses, crossbars or 2D-NoC links. The TSV-Hub allows migration of traditional 2D interconnects towards the 3D stack while benefiting from a reduced TSV count and reuse of existing IP blocks and interconnection schemes. Furthermore, the TSV-Hub approach is also advantageous under interconnect resilience considerations. An incorporated switchbox enables dynamic protection switching for several faulty TSVs. Moreover, it can even cope with situations when more than the number of spare TSVs becomes defective. By means of a case study with two independent AXI interconnects, we could show an area reduction in the range of at least 10% for a TSV size of 10μm and conservatively estimated the reliability improvement by one order of magnitude in comparison to a direct link interconnection.

High speed imaging using a capacitive division technique

The charge division technique is a simple concept used in photon-counting imaging detectors to determine one or two-dimensional event coordinates by location of the centroid of the charge cloud generated in the detector. Traditional devices, such as the resistive anode and wedge-and-strip anode, utilize resistive and geometric methods respectively to implement this technique, enabling them to achieve reasonably good spatial resolution at moderate event rates using a low electronic channel count.We describe the Capacitive Division Image Readout (C-DIR), a simple method of implementing charge division readout with major performance advantages and which is simple and economical to construct. C-DIR utilizes three elements; (i) a resistive layer providing event charge localization and DC signal current return path, (ii) a dielectric substrate which provides electrical isolation from the detector voltages and capacitively couples the event transient signal to the third element, (iii) an array of capacitively coupled electrodes which divides the signal among several charge measurement nodes. The purely capacitive signal paths have high bandwidth and present a low capacitive load to the preamplifiers, allowing an unprecedented combination of excellent event time and spatial resolution.We present simulations and experimental results demonstrating the performance advantages of the device and discuss various readout design alternatives, optimized electronics and potential applications.

Optimized step-stacked-routing ESD diode and its effects on LNA minimum noise figure

Low capacitance loading is a continuous demand and challenge for ESD device design. In this research, an inter-digital ESD diode realized in TSMC 0.18um process is optimized and verified. The diode is capable of passing 7κV HBM with 190fF capacitance loading for dual diode protection scheme. Using the novel Step-Stacked-Routing technique, the capacitance is reduced by 18%. The effect on LNA minimum noise figure of this diode is analyzed and simulated with the extracted small signal model.

InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD protection circuits

This paper presents design considerations and implementation of InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD protection circuits. The inherit benefits of both bandwidth and ESD robustness of distributed amplifiers are first compared to those of single-ended feedback amplifiers. Next, novel on-chip ESD protection circuits are introduced, featuring low capacitance loading for wide bandwidth, low leakage, and good linearity under high RF power. This paper discusses the principle of operation, ESD performance, and RF loading of the ESD protection circuits. The RF performance and ESD robustness of the distributed amplifier with the ESD protection circuits are also presented.

Design and application of CMOS bulk input scheme

This work presents CMOS bulk input differential logic (BIDL) circuits. The bulk input scheme is applied to enable bulk terminals to receive signals. A boost circuit is employed to the bulk terminal of an input device. A multiple-input boost circuit is also developed to improve the flexibility of logic design. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to a low parasitic resistive and capacitive load. The BIDL has better speed and power performance than conventional differential logic circuits. The flexibility of the logic design is greatly improved. The BIDL is applied to a divide-by-128/129 frequency synthesizer using a 0.25-/spl mu/m CMOS process. Measurement results of the test chip indicate that the operating frequency is 2 GHz at a supply voltage of 2.5 V.

A double-sampling SC-resonator for low voltage bandpass ΔΣ -modulators

In this paper, a novel double-sampling switched-capacitor (SC)-resonator with high performance is proposed. The quality factors of the resonators, high notch Q-value and the accurate notch frequency, are analyzed at the transfer function level. Furthermore, their effect on the quantization noise shaping in the implementation of the BP /spl Delta//spl Sigma/-modulator is explained. Discrete-time resonator topologies are discussed and the double delay resonator structure is shown to have potential to implement high performance resonators. A double-sampling switched-capacitor resonator is presented with comparisons to reported structures. The nonidealities are analyzed in the light of the preceding theoretical scrutiny. The structure is found to be very insensitive to imperfections of the analog circuits and it has a low capacitive load leading to a low power consumption. Finally, a BP /spl Delta//spl Sigma/-modulator using the proposed resonator is presented along with behavioral level simulation results.

A Simple Random Noise Generator Employing Metal-Oxide-Semiconductor-Field-Effect-Transistor Channel kT/C Noise and Low-Capacitance Loading Buffer

An eight-transistor random noise generator employing a new circuit architecture has been developed. A compact two-transistor thermal noise source comprising a complementary metal-oxide-semiconductor (CMOS) inverter is proposed as a viable alternative to the area consuming conventional resistive noise source. The total extracted noise power is increased by reducing the effective capacitance at the output of the thermal noise source through the use of a unity-gain low-capacitance loading buffer. A wide-bandwidth high-noise-power random noise generator comprising the CMOS inverter noise source, a CMOS source follower as a low-capacitance loading buffer and a cascode amplifier as a high-gain stage, was fabricated and its noise generation capability experimentally verified. It has a very simple circuit configuration and is fully compatible with current VLSI technology, thus making it a promising candidate for integration of multiple random noise generators on a chip.

Ternary dynamic differential no-race logic

A digital dynamic switching technique for CMOS that can realize ternary functions is introduced. Besides the ease of the design of the switching functions, the positive properties of a low capacitive load, a high noise margin and the need for a standard CMOS process technology should be emphasized. Furthermore, no buffering between cascaded gates is necessary. The effectiveness of the ternary switching technology in contrast to a binary one is demonstrated by the example of an array multiplier.

Errors in measuring laser radiation energy by using multielement matrix measurement facilities

istic may be the drop in R. when the level of illumination is increased. J The results obtained show that to obtain maximum linear dynamic range in a photodiode in pulsed photometers it is necessary to select the photoreceivers in advance. FD-24K photodiodes can be selected by measuring the speed of response of the receiver or the photodiode resistance in the forward direction. It is desirable to select the photodiodes using the latter method when measuring pulse energy with a resistance R < 70 ~2 (Uo = 3 V). The ED-8K and Fon photodiodes must be used with a comparatively low capacitive load, while the Rubin germanium photodiode can be employed successfully with a capacitive load of less than 0.01 ~E.