Low Area Occupation Research Articles

3D printed reticular manganese dioxide cathode with high areal capacity for aqueous zinc ion batteries

The integration of electronic devices has placed increasing demands on the low area occupancy, high areal capacity and safety of energy storage devices. Aqueous zinc ion batteries are expected to be used in highly integrated precision electronics due to their high safety, environmentally friendly and low cost advantages. However, the conventional coating method limits the structure and the areal capacity of electrodes. To address this issue, we design and fabricate a novel 3D printed reticular MnO2 self-supporting cathode. Ascribed to the high mass loading and reticular structure of the reticular MnO2 cathode, the AZIBs deliver a high areal capacity (3.43 mAh cm−2 at 2 mA cm−2). It is demonstrated that the reticular structure facilitates electrolyte storage and rapid diffusion of Zn2+ and reduces charge transfer impedance. Furthermore, the 3D printing technology can realize layer-by-layer printing of electrodes. The areal capacity of the two-layer 3D reticular MnO2 cathode is almost twice as high as that of 3D reticular MnO2. This work indicates the great potential of 3D printing technology in the design and fabrication of high-load electrodes with a high areal capacity and customized shapes.

Heat pipe-cooled highly-concentrated multi-junction solar cell

Concentrator photovoltaic (CPV) systems have proven the capability of competing with traditional photovoltaic (PV) systems due to their high efficiency and low area occupancy. Such CPV systems require efficient heat removal auxiliary systems, especially for medium and high optical concentration ratios. Operating a CPV system under a high optical concentration (ratio > 200 X) might require active cooling techniques, which have high operating costs and maintenance. On the other hand, heat pipes (HPs) are widely used in electronic devices for cooling purposes. This work discusses the possibility of operating a CPV system coupled with HPs as a passive cooling technique. Two different HPs with different lengths are used to compare cooling efficiency. Each HP length was tested either in a single or double configuration. Long HPs showed better heat removal compared to a traditional fin-cooling system. CVP cooling with HP systems enhanced the entire electrical output of the cell, mainly at high optical concentration ratios.

Edge-sorter: A hardware sorting engine for area & power constrained edge computing devices

In recent years, hardware sorters have been an attracted topic for researchers. Since hardware sorters play a crucial role in embedded systems, several attempts have been made to efficiently design and implement these sorters. Previous state-of-the-art hardware sorters are not suitable for embedded edge computing devices because they (1) consume high power, (2) occupy high area, (3) work for limited data-width numbers, (4) require many memory resources, and (5) finally, their architecture is not scalable with the number of input records. This paper proposes a hardware sorter for edge devices with limited hardware resources. The proposed hardware sorter, called Edge-Sorter, processes 4 bits of input records at each clock cycle. Edge-Sorter utilizes the unary processing in its main processing core. Edge-Sorter has valuable attributes compared to previous state-of-the-art techniques, including low power consumption, low area occupation, sorting numbers without storing their indices, sorting numbers with arbitrary data-width, and scalable with the number of input records. The proposed approach is evaluated and compared with previous state-of-the-art techniques with two different implementation and synthesis environments: Xilinx Vivado FPGA-based and Synopsys Design Compiler 45-nm ASIC-based. The Synthesis results of both environments indicate that both Edge-Sorter techniques reduces area and power consumption on average by 80% and 90%, respectively compared to previous techniques.

A 0.053 mm2 10-bit 10-ks/s 40-nW SAR ADC with pseudo single ended switching procedure for bio-related applications

This paper presents a power and area efficient pseudo single ended switching ADC for portable biomedical signal monitoring applications. The switching method features an 8-bit binary-weighted DAC array with a novel layout method called limited bottom-plate routing (LBPR) maintaining both feasibility and symmetry, a dynamic biased comparator and dynamic control logic. As a result, the proposed ADC saves 96.7% power consumption and 87.5% area occupation compared with conventional SAR ADC. Also, a novel DAC array layout method is promoted maintaining both feasibility and symmetry. A prototyped chip including a proposed ADC is fabricated in a 0.13 μm CMOS process. On condition of 0.6 V supply voltage and 10 kS/s sampling rate, the measured signal-to-noise-distortion (SNDR) and spurious free dynamic range (SFDR) are 57.8 dB and 64.3 dB, respectively. Besides, the ADC consumes only 40 nW power and 0.053 mm2 area achieving a figure-of-merit (FoM) of 6.26 fJ/conversion-step. Low power and low area occupation make it a good candidate for biomedical signal monitoring applications.

A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM

This brief presents a parallel magnetoresistive random access memory (MRAM)-based strong physical unclonable function (MPUF). The proposed MPUF leverages fabrication-induced process variations of magnetic tunnel junction (MTJ) and compares the resistance of MRAM cells to obtain a 1-bit response value. Contrary to arbiter PUF, the proposed MPUF achieves maximum security by satisfying strict avalanche criterion (SAC) property, and its secrecy capacity increases linearly with CRPs. Moreover, an array selection circuit (ASC) is proposed, which injects strong non-linearity into the PUF response and improves the robustness against machine learning (ML)- based modeling attacks. The proposed MPUF demonstrates high reliability, uniqueness, and uniformity with mean intra and inter-hamming distance (HD) of 0.447% and 49.76%, respectively. The robustness evaluation of the proposed MPUF against ML attacks, such as multilayer perceptron (MLP), linear regression (LR), and support vector machine (SVM), shows that it is resistant to these attacks, with ML-attack prediction accuracy of less than 79.7% for the basic two-array MPUF and less than 53.8% for the four-array MPUF with ASC. Moreover, compared to existing PUFs, the proposed MPUF has a large CRP space, high energy efficiency, and low area occupancy.

Stochastic Computing Using Amplitude and Frequency Encoding

Stochastic computing (SC) is a type of logic computation based on stochastic bit stream instead of the binary numbers (BNs). It is pseudo-analog computation in the digital domain that can realize multiplication, addition, and complex function computations. In this brief, a new encoding method, referred to as amplitude and frequency encoding (AFE) for SC, is presented. It extends SC to use multibit streams instead of bit streams to represent data. This method still uses the expectation of streams to achieve computation. Compared with the conventional stochastic bit stream, AFE realizes low-latency and low-area occupation than the conventional SC method. The rationality of the circuits is also examined from a mathematical perspective. The hardware logic circuit of AFE SC, including the multiplier, adder, and converter, was designed and implemented by a field-programmable gate array (FPGA). In addition, the latency of the computing, area, and precision of AFE SC was measured based on the FPGA board.

Ferroelectric-based synapses and neurons for neuromorphic computing

Abstract The shift towards a distributed computing paradigm, where multiple systems acquire and elaborate data in real-time, leads to challenges that must be met. In particular, it is becoming increasingly essential to compute on the edge of the network, close to the sensor collecting data. The requirements of a system operating on the edge are very tight: power efficiency, low area occupation, fast response times, and on-line learning. Brain-inspired architectures such as spiking neural networks (SNNs) use artificial neurons and synapses that simultaneously perform low-latency computation and internal-state storage with very low power consumption. Still, they mainly rely on standard complementary metal-oxide-semiconductor (CMOS) technologies, making SNNs unfit to meet the aforementioned constraints. Recently, emerging technologies such as memristive devices have been investigated to flank CMOS technology and overcome edge computing systems’ power and memory constraints. In this review, we will focus on ferroelectric technology. Thanks to its CMOS-compatible fabrication process and extreme energy efficiency, ferroelectric devices are rapidly affirming themselves as one of the most promising technologies for neuromorphic computing. Therefore, we will discuss their role in emulating neural and synaptic behaviors in an area and power-efficient way.

Low power switched-resistor band-pass filter for neural recording channels in 130nm CMOS

In this work, we present a low-power 2nd order band-pass filter for neural recording applications. The central frequency of the passband is set to 375Hz and the quality factor to 5 to properly process the neural signals related to the onset of epileptic seizure, and to strongly attenuate all the out of band biological signals and electrical disturbances. The biquad filter is based on a fully differential Tow Thomas architecture in which high-valued resistors are implemented through switched high-resistivity polysilicon resistors. A supply voltage as low as 0.8V and MOS transistors operating in the sub-threshold region are exploited to achieve a power consumption as low as 170nW, when driving a 1pF load capacitance. The filter exhibits a tuning range of the resonance frequency from 200Hz to 400Hz, and an area footprint of only 0.021 mm2. Very low power consumption and area occupation are key specifications for integrated, multiple-sensors, neural recording systems.

Memory-Efficient Polar Decoders

Polar codes have gained a great amount of attention in the past few years, since they can provably achieve the capacity of a symmetric channel with a low-complexity encoding and decoding algorithm. As a result, polar codes have been selected as a coding scheme in the 5th generation wireless communication standard. Among different decoding schemes, successive-cancellation (SC) and SC list decoding yield good trade-off between error-correction performance and hardware implementation cost. However, both families of algorithms have large memory requirements. In this paper, we propose a set of novel techniques that aim at reducing the high-memory cost of SC-based decoders. These techniques are orthogonal to the specific decoder architecture considered, and can be applied on top of existing memory reduction techniques. We have designed and implemented different polar decoders on FPGA and also synthesized them in 65 nm TSMC CMOS technology to verify the effectiveness of the proposed memory reduction techniques. The benchmark decoders yield comparable or lower area occupation than the state of the art: the results show that the proposed methods can save up to 46% memory area occupation and 42% total area occupation compared with benchmark SC-based decoders.

Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage.

Multichannel neural recording system based on family ASICs processed in submicron technology

In this paper we present a measurement system for in vivo multichannel recordings of the electrophysiological activity of brain tissue. The system consists of penetrating Microelectrode Array (MEA), three versions of a Conditioning Module each equipped with different Application Specific Integrated Circuits (ASIC), Digitizer and PC Application for recorded data presentation and storage. The MEA consists of 64 15μm diameter microelectrodes. The multichannel ASICs amplify and filter field and action potential signals. The custom-made Digitizer Module simultaneously acquires data from all channels with a 14kS/s sample rate and 12bit resolution. The resulting byte stream (about 2MB/s) is transmitted to the PC via USB (Universal Serial Bus). Eventually the measurement data is decoded, presented to the system user and stored on a HDD. Preliminary system tests confirm its excellent performance (low input refereed noise, low power consumption, low area occupancy, ability of Action Potentials/Local Field Potentials separation). Our system equipped with multichannel ASICs meets requirements of many different neurobiology experiments.

A 7-bit 500 kS/s 1 V micro-power SAR A/D converter for pixel systems

The design and measurement results of a micro-power successive approximation charge redistribution ADC implemented in CMOS 180nm technology are presented. The project has been optimized for very low area occupancy in order to utilize it in multichannel neural signal recording pixel systems for future application. The design has been fabricated, experimentally characterized and it exhibits good performance, especially from the silicon area occupation point of view. The presented converter achieves 500kS/s sampling rate with ENOB of 6.54 at 4.45μW and occupies only 90μm×95μm of silicon area.

A Discussion of a 60GHz Meander Slot Antenna for an RFID TAG with Lumped Element

In this paper, a novel approach to design an antenna for a transponder in radio frequency identification (RFID) is proposed. This approach is based on using a meander slot patch with a coplanar waveguide excitation (CPW). The RFID frequency chosen is the free 60 GHz band. The proposed circuit does not require complex package or bonding, thanks to the on-chip antenna, and it does not need battery. This technology is characterized by the low-cost, low-weight and low-area occupation. These particular specifications are important of this micro-RFID, especially if produced in large scale for the mass-market. Since the model of antennas in silicon technology is one of the main challenges, particularly for this proposal. The structure is simulated by using Computer Simulation Technology (CST). The antenna size is 1.95 * 1.99 mm2.This proposed antenna presents again which means a possibility to increase the readable range.

Life cycle assessment of biomass production in microalgae compact photobioreactors

AbstractThis paper presents a life cycle assessment (LCA) of industrial scale microalgae biomass production in compact photobioreactor (PBR) systems (2 × 5 × 8 m) for supplying biofuel/electricity generation processes and synthesis of new materials. Other objectives are as follows: (i) to compare the impact of various raw materials, substances, and services; and (ii) to evaluate environment‐relevant aspects of the proposed system as compared to microalgae raceway ponds. The life cycle inventory assessment shows that (i) only atmospheric CO2 is used for PBR microalgae cultivation, whereas in raceway ponds, injection of CO2 from fossil origin is largely required to allow for microalgae growth; and (ii) the PBR daily production rate of dry biomass is currently at 1.5 kg m−3 day−1 for each PBR, which is 12.82 times larger than the reported average 0.117 kg m−3 day−1 raceway ponds production. It is found that in general the association of the effects of the production of steel, PVC, and the packaging contribute to more than 85% of the total impact in each analyzed category. Therefore, to achieve PBR biomass production impact reduction and sustainability, PVC and steel utilization need to be minimized, as well as packaging materials. Based on the PBR LCA results, that is, due to no CO2 injection from fossil origin and low area occupation, it is expected that high density production of truly renewable microalgae biomass could be obtained from PBR systems.

Four Channel, 40 ps Resolution, Fully Integrated Time-to-Amplitude Converter for Time-Resolved Photon Counting

Recently, a growing interest has arisen about the time-correlated single photon counting (TCSPC) technique, that allows the analysis of fast and weak light waveforms with a time resolution in the picosecond order. Since TCSPC basically consists of the measurement of the arrival time of a photon, a high resolution and high linearity time measurement block is of the utmost importance; moreover, the use of multianode Photo Multiplier Tube and of single photon avalanche diode arrays led to the development of multichannel acquisition systems, where the time measurement block has to be integrated to reduce both cost and area. We have designed and fabricated a four channel fully integrated time-to-amplitude converter (TAC), built in 0.35 μm Si-Ge technology, characterized by an excellent time resolution (less than 50 ps full width half maximum), low differential nonlinearity (better than 0.02 LSB peak-peak and 0.0003 LSB rms), high counting rate (16 MHz), low and constant power dissipation (50 mW) and low area occupation (2.58 × 1.28 mm2 ). Moreover, the very low crosstalk ( -115 dB) between channels, together with low power and low area makes the converter suitable for large scale multi-channel acquisition chains.

FPGA Based A New Low Power and Self-Timed AES 128-bit Encryption Algorithm for Encryption Audio Signal

This paper presents, a low power 128-bit Advanced Encryption Standard (AES) algorithm based on a novel asynchronous self-timed architecture for encryption of audio signals. An asynchronous system is defined as one where the transfers of information between combinatorial blocks without a global clock signal. The self-timed architectures are asynchronous circuits which perform their function based on local synchronization signals called hand shake, independently from the other modules. This new architecture reduced spikes on current consumption and only parts with valid data are working, and also this design does not need any clock pulse. A combinational logic based Rijndael S-Box implementation for the Substitution Byte transformation in AES is proposed, its low area occupancy and high throughput therefore proposed digital design leads to reduction in power consumption. Mix-columns transformation is implemented only based on multiply- by-2 and multiply-by-3 modules with combinational logic. The proposed novel asynchronous self-timed AES algorithm is modeled and verified using FPGA and simulation results from encryption of sound signals is presented, until original characteristics are preserved anymore and have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. The achieved power consumption is 283 mW in clock frequency of 100 MHz.

A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS

A successive approximation analog-to-digital converter (ADC) architecture is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. While targeting medium resolutions and speed, the threshold configuring (TC) ADC achieves low power consumption and small area occupation by using a fully dynamic configurable comparator and an asynchronous controller, with no need for a highly linear feedback D/A converter. The TC-ADC embeds its own references, and relies on a minimal amount of passive components or calibration loops. A 6-bit prototype implementation in 90-nm digital CMOS technology achieves 32-dB SNDR at 50 MS/s and consumes 240 μW from 1-V analog and 0.7-V digital supplies. This results in 150 fJ/conversion-step in a core area occupation of only 0.0055 mm .

Note: Fully integrated time-to-amplitude converter in Si–Ge technology

Over the past years an always growing interest has arisen about the measurement technique of time-correlated single photon counting TCSPC), since it allows the analysis of extremely fast and weak light waveforms with a picoseconds resolution. Consequently, many applications exploiting TCSPC have been developed in several fields such as medicine and chemistry. Moreover, the development of multianode PMT and of single photon avalanche diode arrays led to the realization of acquisition systems with several parallel channels to employ the TCSPC technique in even more applications. Since TCSPC basically consists of the measurement of the arrival time of a photon, the most important part of an acquisition chain is the time measurement block, which must have high resolution and low differential nonlinearity, and in order to realize multidimensional systems, it has to be integrated to reduce both cost and area. In this paper we present a fully integrated time-to-amplitude converter, built in 0.35 μm Si-Ge technology, characterized by a good time resolution (60 ps), low differential nonlinearity (better than 3% peak to peak), high counting rate (16 MHz), low and constant power dissipation (40 mW), and low area occupation (1.38×1.28 mm(2)).

Monolithic time to amplitude converter for time correlated single photon counting

Time correlated single photon counting techniques allow in depth examinations of very important chemical and biological processes involving complex interactions of biomolecules. Understanding of these processes is of the utmost importance to address vital medical issues such as the origin and growth of tumors. Modern developments of fluorescence analysis techniques require compact, low cost, and high performance instrumentation, and a major path to these goals is the successful integration of the electronics. In this paper we present a fully monolithic time to amplitude converter, built in standard 0.35 microm CMOS technology, characterized by good time resolution (60 ps), low differential nonlinearity (better than 0.5% rms), short dead time (80 ns), low power dissipation (60 mW), and low area occupation (1.8x1.4 mm(2)).

Design of programmable NoC router architecture on FPGA for multi-cluster NoCs

The next generations of massive, parallel and reconfigurable multi-cluster chips need performance and flexibility, requiring new communication schemes. According to this scenario, a programmable router architecture for networks-on-chips is presented. Results indicate that the proposed router has low area occupation, low power consumption and a high data throughput.