A 7-bit 500 kS/s 1 V micro-power SAR A/D converter for pixel systems

Abstract

The design and measurement results of a micro-power successive approximation charge redistribution ADC implemented in CMOS 180nm technology are presented. The project has been optimized for very low area occupancy in order to utilize it in multichannel neural signal recording pixel systems for future application. The design has been fabricated, experimentally characterized and it exhibits good performance, especially from the silicon area occupation point of view. The presented converter achieves 500kS/s sampling rate with ENOB of 6.54 at 4.45μW and occupies only 90μm×95μm of silicon area.