Fault Coverage Loss Research Articles

Increasing the Fault Coverage of a Truncated Test Set

Defect-aware, cell-aware, and gate-exhaustive faults are described by input patterns of subcircuits or cells that are expected to activate defects. Even with single-cycle faults, an\( n \)-input subcircuit can have up to\( 2^n \)faults with unique fault detection conditions, resulting in a large test set. Such a test set may have to be truncated to fit in the tester memory or satisfy constraints on test application time. In this case, a loss of fault coverage is inevitable. This article considers the test set denoted by\( T_1 \)obtained after truncating a larger test set denoted by\( T_0 \). Suppose that the truncation reduces the set of detected faults from the set denoted by\( D_0 \)to the set denoted by\( D_1 \). The procedure described in this article modifies the tests in\( T_1 \)to gain the detection of faults from\( D_0 \)\( \setminus \)\( D_1 \), even at the cost of losing the detection of faults from\( D_1 \). The goal is to reduce the fault coverage loss by computing a test set denoted by\( T_2 \)that detects a set of faults denoted by\( D_2 \)such that\( |T_2| = |T_1| \)and\( |D_2| \gt |D_1| \). Experimental results for benchmark circuits demonstrate the ability of the procedure to increase the coverage of gate-exhaustive faults over several iterations.

Tri-level regression testing using nature-inspired algorithms

A software needs to be updated to survive in the customers’ ever-changing demands and the competitive market. The modifications may produce undesirable changes that require retesting, known as regression testing, before releasing it in the public domain. This retesting cost increases with the growth of the software test suite. Thus, regression testing is divided into three techniques: test case prioritization, selection, and minimization to reduce costs and efforts. The efficiency and effectiveness of these techniques are further enhanced with the help of optimization techniques. Therefore, we present the regression testing using well-known algorithms, genetic algorithm, particle swarm optimization, a relatively new nature-inspired approach, gravitational search algorithm, and its hybrid with particle swarm optimization algorithm. Furthermore, we propose a tri-level regression testing, i.e., it performs all the three methods in succession. Nature-inspired algorithms prioritize the test cases on code coverage criteria. It is followed by selecting the modification-revealing test cases based on the proposed adaptive test case selection approach. The last step consists of the removal of redundant test cases. The hybrid algorithm performed well for the average percentage of statement coverage, and the efficiency of genetic algorithm and particle swarm optimization is better comparatively. The proposed test case selection method can select at least 75% modification-revealing test cases using nature-inspired algorithms. Additionally, it minimizes the test suite with full statement coverage and almost negligible fault coverage loss. Overall, the simulation results show that the proposed hybrid technique outperformed the other algorithms.

Test Compaction by Backward and Forward Extension of Multicycle Tests

Multicycle tests are useful for test compaction even when full scan allows single- or two-cycle tests to be used. To avoid sequential test generation, multicycle tests can use the test data (scan-in states and primary input vectors) from a single- or two-cycle test set, possibly modified to make it more suitable for multicycle tests. However, the modification process requires repeated fault simulation to prevent a loss of fault coverage. This brief observes that the need to modify test data results from the fact that tests are only extended forward to increase their numbers of clock cycles starting from their (modified) scan-in states. The brief observes further that extending tests backward is a more computationally efficient way of obtaining multicycle tests with modified test data. The brief defines a new type of multicycle test to increase the effectiveness of backward extension and describes a test compaction procedure based on backward and forward extension. It presents experimental results for gate-exhaustive faults, requiring large numbers of tests, in benchmark circuits.

Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults

The use of both broadside (launch-on-capture) and skewed-load (launch-on-shift) tests for delay faults results in increased delay fault coverage and better test compaction than the use of a single test type. Two-cycle broadside and skewed-load tests differ in the sequence of length two applied to the scan-enable input between the scan-in and scan-out operations of a test. Considering a circuit with a single clock domain, the question that this article attempts to answer is whether it is possible to generate a complete test set for transition faults where all the tests use the same scan-enable sequence of length three or more. The use of a single scan-enable sequence simplifies the test application process. Experimental results demonstrate that there is a significant number of benchmark circuits for which a test set with a single scan-enable sequence achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests. For other benchmark circuits, a small loss in transition fault coverage compared with the use of both test types allows a single scan-enable sequence to be used.

Predicting ${X}$ -Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning Approach

Digital circuits are often prone to suffer from uncertain timing, inadequate sensor feedback, limited controllability of past states or inability of initializing memory-banks, and erroneous behavior of analog-to-digital converters, which may produce an unknown ( ${X}$ ) logic value at various circuit nodes. Additionally, many design bugs that are identified during the post-silicon validation phase manifest themselves as ${X}$ -values. The presence of such ${X}$ -sources on certain primary or secondary inputs of a logic circuit may cause loss of fault-coverage of a test set, which, in turn, may impact its reliability and robustness. In this paper, we provide a mechanism for predicting the sensitivity of ${X}$ -sources in terms of loss of fault-coverage, on the basis of learning only a few structural features of the circuit that are easy to extract from the netlist. We show that the ${X}$ -sources can be graded satisfactorily according to their sensitivity using support vector regression, thereby obviating the need for costly explicit simulation. Experimental results on several benchmark circuits demonstrate the efficacy, speed, and accuracy of prediction.

ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction

Aliasing in test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing mostly require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc.In contrast to this standard approach, we propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing for any compactor used, thus without need of the compactor modification or redesign. This is achieved by constraining the test pattern generation process (ATPG), so that patterns exhibiting no aliasing are produced directly. Aliasing in both the spatial and temporal compactors is assumed.The method is based on modification of very basic SAT-based ATPG principles, thus any SAT-based ATPG can be used for its purpose. Also, the method is general enough to be applicable to any compactor design.We demonstrate our method on MISR compactors based on LFSR and cellular automata, using the single stuck-at fault model. Our method is able to find a test with zero aliasing and complete fault coverage for smaller compactors than a conventional, unguided ATPG. Thus, the area overhead of the compactor can be reduced, while the complete fault coverage is preserved.

Multicast Testing of Interposer-Based 2.5D ICs

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a major challenge to test 2.5D ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this article, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. By considering the trade-off between test-application time, test-power budget, and test quality, the proposed technique provides test schedules with minimum test-application time under constraints on power consumption and fault coverage. Compared to previous work, the proposed technique can reduce test-application time by up to 53.4 for benchmark designs while achieving higher fault coverage. Since the loss in fault coverage due to multicast testing is extremely small, we can use top-off patterns to achieve full fault coverage for the dies at negligible additional cost.

Test Pattern Modification for Average IR-Drop Reduction

This paper presents a novel technique that modifies automatic test pattern generation test patterns to reduce time-averaged IR drop of a test pattern. We propose a fast average IR drop estimation, which is very close to the time-averaged IR drop of time-consuming transient simulation ( $R^{2} =0.99$ ). We calculate the contribution of every node to these nodes inside IR-drop hotspot so that we can effectively modify only a few don’t care bits in the test patterns to reduce IR drop. The experimental results show that our technique successively reduces time-averaged IR drop by 10% with almost no fault coverage loss and no test pattern inflation.

Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array

Static random access memories (SRAM) are a major constituent in high performance microprocessors and systems-on-a-chip. With scaling of technology, manufacturing process variations in SRAMs are of significant concern. SRAM cells that are marginal due to process variations suffer from stability issues where random thermal noise and random telegraph noise (RTN) become determinant in memory state. This introduces uncertainty in testing, where passing a test does not necessarily mean that SRAM is good. A marginal cell may pass testing, but fail during operation. To address this problem, we introduce a new metric for probabilistic fault coverage. We present simulation methods for measuring such coverage and propose N-detect and multilevel wordline (WL) voltage techniques to increase the detection probability of marginal cells. We demonstrate the benefit of these testing approaches on a sample SRAM array, designed in 32 nm predictive technology models. To simulate marginal cells, we oversample the tail of the process variations distribution. Transient noise simulations show that thermal noise can lead to a fault coverage loss of 20% and RTN can lead to a maximum fault coverage loss of up to 75%. N-detect technique achieves close to a 100% fault coverage at ${n}\,\, {=} 100$ for thermal noise and ${n}\,\,{=} 70$ for RTN. Multilevel WL technique requires 20–30 mV boost in WL voltage during read test to achieve near ideal fault coverage at minimal yield loss. A combination of these techniques is shown to be effective in increasing fault coverage with a tradeoff between test time and yield loss.

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality (TQ) loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers tradeoff flexibility between test application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase TQ when considering systematic variations. Through SPICE simulations, we show complete recovery of the TQ lost due to PDNs. The proposed method is robust, sustaining 80.3%–98.6% of the achieved TQ under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on TQ and offers a unified test solution for both ring and grid power gating styles.

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS’89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing

During an at-speed scan-based test, excessive capture power may cause significant current demand, resulting in the IR-drop problem and unnecessary yield loss. Many methods address this problem by reducing the switching activities of power-risky patterns. These methods may not be efficient when the number of power-risky patterns is large or when some of the patterns require extremely high power. In this paper, we propose discarding all power-risky patterns and starting with power-safe patterns only. Our test generation procedure includes two processes, namely, test pattern refinement and low-power test pattern regeneration. The first process is used to refine the power-safe patterns to detect faults originally detected only by power-risky patterns. If some faults are still undetected after this process, the second process is applied to generate new power-safe patterns to detect these faults. The patterns obtained using the proposed procedure are guaranteed to be power-safe for the given power constraints. To the best of our knowledge, this is the first method that refines only the power-safe patterns to address the capture power problem. Experimental results on ISCAS'89 and ITC'99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detected by the low-power test generation process. Furthermore, the required test data volume can be reduced by 12.76% on average with little or no fault coverage loss.

Low power logic BIST with high test effectiveness

Excessive test power has been a serious concern in BIST techniques. Shift power consumption can be significantly reduced by increasing the correlation among adjacent test data bits. However, this method may cause fault coverage loss. This paper presents a novel low power BIST scheme that reduces toggle probability of the scan input data while only shifting out part of capture responses for fault analysis and using the rest of capture responses as new test data. Using part of capture responses as test data can improve uniform distribution of 1s and 0s in test stimulus bits and thus result in high test effectiveness. Experimental results on larger benchmark circuits of ISCSAS89 and ITC99 show that the proposed strategy can reduce significantly test power while suppressing test coverage loss.

Undetectable transition faults under broadside tests with constant primary input vectors

In a broadside test, a scan-in operation is followed by two functional clock cycles where primary input vectors, denoted by v0 and v1, are applied. Because of tester limitations that prevent the primary input vectors from being changed at speed, broadside tests are computed under the constraint where v0=v1. This results in a loss of delay fault coverage. This study develops a fast procedure for identifying transition faults that are undetectable by broadside tests under the constraint v0=v1. Faults that are undetectable because of this constraint are undetectable because of tester limitations and not because of the logic in the circuit. These faults may be able to affect the circuit during functional operation, when the primary input vectors are unconstrained. In this case the faults are important to detect. A fast procedure for identifying undetectable transition faults under the constraint v0=v1 provides a quantitative measure of the effect of this constraint on the achievable fault coverage without performing test generation. If it turns out that the effect on fault coverage is unacceptable, other solutions may be used without first performing test generation.

MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing

Scan shift power can be reduced by activating only a subset of scan cells in each shift cycle. In contrast to shift power reduction, the use of only a subset of scan cells to capture responses in a cycle may cause capture violations, thereby leading to fault coverage loss. In order to restore the original fault coverage, new test patterns must be generated, leading to higher test-data volume. In this paper, we propose minimum-violations partitioning, a scan-cell clustering method that can support multiple capture cycles in delay testing without increasing test-data volume. This method is based on an integer linear programming model and it can cluster the scan flip-flops into balanced parts with minimum capture violations. Based on this approach, hierarchical partitioning is proposed to make the partitioning method routing-aware. Experimental results on ISCAS'89 and IWLS'05 benchmark circuits demonstrate the effectiveness of our method.

Functional fault models for non-scan sequential circuits

The paper presents two functional fault models that are applied for functional delay test generation for non-scan synchronous sequential circuits: the pin pair state (PPS) fault model and the pin pair full state (PPFS) fault model. The PPS fault model deals with the pairs of stuck-at faults on the primary inputs and the primary outputs, as well as, with the pairs of stuck-at faults on the previous state bits and the primary outputs. The PPFS fault model encompasses the PPS model, and additionally deals with the pairs of stuck-at faults on the primary inputs and the next state bits, as well as, with the pairs of stuck-at faults on the previous state bits and the next state bits. The main factor in assessing the quality of obtained test sequences was the transition fault coverage at the gate level of the selected according to the appropriate fault model test sequences from the generated randomly ones. The experimental results demonstrate that the implementation using presented functional fault models allow selecting the test sequences from the initial test set without the loss of transition fault coverage in many cases, and the number of the selected test sequences is much lesser than that of the initial test set. This result demonstrates that the functional delay test can be generated using the presented functional delay fault models before structural synthesis of the circuit.

Row-linear feedback shift register-column X -masking technique for simultaneous testing of many-core system chips

This study presents a row-linear feedback shift register-column (RLC) masking technique that is capable of handling many unknowns in the test responses. The proposed technique takes advantage that most unknowns are locally clustered after the test compactor. With three novel masking mechanisms [direct row, direct column and linear feedback shift register (LFSR) column masking], RLC masks all unknowns in test responses using a very short LFSR. Experiments on a real design show that the proposed technique is able to mask up to 7.38% unknowns with only 0.61% fault coverage loss. By providing a very high test response compaction ratio, RLC masking technique enables massive parallel testing of many-core system chips.

Definition and generation of partially-functional broadside tests

Functional and pseudo-functional broadside tests were defined to address the fact that testing a circuit under non-functional operation conditions, which are made possible by scanning in unreachable states, may result in overtesting or unnecessary yield loss. One of the reasons cited for overtesting is the high switching activity possible with unreachable states. Functional broadside tests allow only reachable states as scan-in states in order to address this issue. However, the exclusive use of functional (or pseudo-functional) broadside tests may result in a loss of fault coverage, which may be a concern for the long-term reliability of the chip. To address this issue, a new class of tests is defined, which is referred to as partially-functional broadside tests. The definition of a partially-functional broadside test allows the scan-in state to be an unreachable state. It measures the amount of deviation from functional operation by considering the minimum Hamming distance between the scan-in state and a reachable state. With a smaller minimum Hamming distance, the number of state variables that operate under functional operation conditions is likely to be higher. A procedure for computing what are called partially-reachable states, which are used for generating partially-functional broadside tests is described. We demonstrate that the switching activity under partially-functional broadside tests is close to that of functional broadside tests. Thus, partially-functional broadside tests operate the circuit under conditions that are close to functional operation conditions, helping to avoid overtesting because of high switching activity while improving fault coverage.

Systematic Software-Based Self-Test for Pipelined Processors

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion

Functional broadside tests were defined to address overtesting that may occur due to high peak current demands when tests for delay faults take the circuit through states that it cannot visit during functional operation (unreachable states). The fault coverage achievable by functional broadside tests is typically lower than the fault coverage achievable by (unrestricted) broadside tests. A solution to this loss in fault coverage in the form of observation point insertion is described. Observation points do not affect the state of the circuit. Thus, functional broadside tests retain their property of testing the circuit using only reachable states to avoid overtesting due to high peak current demands. However, the extra observability allows additional faults to be detected. A procedure for observation point insertion to improve the coverage of transition faults is described. Experimental results are presented to demonstrate that significant improvements in transition fault coverage by functional broadside tests is obtained.