Loop Unrolling Techniques Research Articles

IMPLEMENTATION FPGA BASED IMPLEMENTATION OF 128-BIT AES ALGORITHM USING VHDL

In current world of computations, data encryption is of prominent importance. Many algorithms were developed for data encryption and decryption to prevent hacking. The Advanced Encryption Standard (AES) is one of the data encryption techniques. Two famous kinds of hardware implementation techniques are pipelining and loop-unrolling techniques. In pipelining, registers are inserted between each combinational processing element so that each input data block can be processed simultaneously in each processing element. In this work, a pipelined implementation of AES encryption algorithm is developed. The number of rounds of AES-128 encryption is 10 and an architecture implementing this cipher is called fully pipelined, when all data blocks of 10 rounds can be processed simultaneously. In the loop-unrolling technique one or multiple rounds of the algorithm are processed in the same clock cycle. Here only one round of the algorithm is implemented as a combinational processing element and a data register is also used to store the result obtained in the previous clock cycle. In this work, a128-bit AES is implemented and for each round of AES encryption, a different sub-key is used as the round key, which is produced by the key schedule algorithm based on the loop-unrolled technique, to produce the required sub-key for each round is done. The no of I/O, Slices in the proposed work are 386, 229 respectively with Spartan6 fpga with a minimum period of 5.813ns,maximum Frequency of 172.031MHz, minimum input arrival time before clock of 4.823ns,maximum output required time after clock of 5.588ns, throughput of 2.2Gbps. The no of I/O, Slices are 387, 264 respectively with Artix7 fpga with a minimum period of 3.397ns, maximum Frequency of 294.366MHz, minimum input arrival time before clock of 1.649ns, maximum output required time after clock of 1.669ns, throughput of 3.77Gbps.

Roofline-Model-Based Design Space Exploration for Dataflow Techniques of CNN Accelerators

To effectively compute convolutional layers, a complex design space must exist (e.g., the dataflow techniques associated with the layer parameters, loop transformation techniques, and hardware parameters). For efficient design space exploration (DSE) of various dataflow techniques, namely, the weight-stationary ( WS ), output-stationary ( OS ), row-stationary ( RS ), and no local reuse ( NLR ) techniques, the processing element (PE) structure and computational pattern of each dataflow technique are analyzed. Various performance metrics are calculated, namely, the throughput (in giga-operations per second, GOPS), computation-to-communication ratio ( CCR ), on-chip memory usage, and off-chip memory bandwidth, as closed-form expressions of the layer and hardware parameters. In addition, loop interchange and loop unrolling techniques with a double-buffer architecture are assumed. Many roofline model-based simulations are performed to explore relevant dataflow techniques for a wide variety of convolutional layers of typical neural networks. Through simulation, this paper provides insights into the trends in accelerator performance as the layer parameters change. For convolutional layers with large input and output feature map ( ifmap and ofmap ) widths and heights, the GOPS of the NLR dataflow technique tends to be higher than that of the techniques. For convolutional layers with low weight and ofmap widths and heights, the RS dataflow technique achieves optimal GOPS and on-chip memory usage. In the case of convolutional layers with small weight widths and heights, the GOPS of the WS dataflow technique tends to be high. In the case of convolutional layers with small ofmap widths and heights, the OS dataflow technique achieves optimal GOPS and on-chip memory usage.

Efficient and high‐throughput application‐specific integrated circuit implementations of HIGHT and PRESENT block ciphers

In this study, low-cost and high-throughput hardware implementations of the HIGHT (HIGh security and lightweigHT) and PRESENT lightweight block ciphers are presented. One of the most complex blocks in the HIGHT algorithm is addition modulo 2 8 . In the proposed structure for implementation of this modular adder, the authors used the structure of Ladner-Fischer, Han-Carlson, Kogge-Stone and Sklansky adders, which are parallel prefix adders with low critical path delay and suitable hardware resources. In the PRESENT block cipher, for two key lengths 80-bit and 128-bit, the S-box is implemented based on an area-optimised combinational logic circuit. In the proposed S-box structure, the number of logic gates and critical path delay is reduced by using Karnaugh mapping and further factorisation. Also, to reduce the latency and increase throughput, the loop unrolling technique is applied in the structures. Implementation results of the proposed architectures in 180 nm complementary metal-oxide-semiconductor technology for different unroll factors are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared to other related works.

High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers

In this paper, low-cost and high-throughput hardware implementations of the HIGHT and PRESENT lightweight block ciphers are presented. One of the most complex blocks in the HIGHT algorithm is addition modulo 28. In the proposed structure for implementation of this modular adder, we used the structure of Ladner-Fischer, Han-Carlson, Kogge-Stone, and Sklansky adders, which are parallel prefix adders with low critical path delay and suitable hardware resources. In the PRESENT block cipher, for two key lengths 80-bit and 128-bit, the S-box is implemented based on an area-optimized combinational logic circuit. In the proposed S-box structure, the number of logic gates and critical path delay are reduced by using the simplification of the Algebraic terms. Also, to reduce the latency and increase throughput, the loop unrolling technique is applied in the structures. We implemented glitch filtering on hardware structures of the HIGHT and PRESENT block ciphers based on the latch-based method to reduce the power consumption. Also, the power analysis, timing attacks and hardware-based countermeasures based on an experimental setup are performed. It is claimed that the current and power profiles are unified and there will be no power consumption difference when encryption operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX50 and Spartan-3 XC3S200 FPGAs for different unroll factors are achieved. The results show the structures are robust against attacks and improvements in terms of execution time, throughput and throughput/area compared to others related works.

Efficient hardware structure for extended Euclidean‐based inversion over

In this study, an efficient hardware structure for implementation of extended Euclidean algorithm (EEA) inversion based on a modified algorithm is presented. In the proposed algorithm, one iteration performs the operations corresponding to two iterations in previously reported EEA-based inversion algorithm. The proposed structure is implemented based on a modified algorithm with low path-delay and hardware consumption. The circuit performs one iteration of the algorithm in one clock cycle. Furthermore, to increase speed and reduce the latency of the structure, the authors applied the loop unrolling technique by replicating the body of the loop. Loop unrolling replaces a loop body by several copies of the body. The authors chose the number of copies based on the trade-off between hardware resources, critical path delay and the number of clock cycles. Therefore, the time and area parameters can be adjusted by different choices. The proposed architecture is simple, low cost and also the number of clock cycles in the structure are reduced compared to existing EEA-based works. The structure over two binary finite fields and has been successfully verified and implemented on Virtex-5 XC5VLX110 field-programmable gate array. The comparison with other previous implementations of the inversion operation verifies that the proposed method has better improvement in terms of area × time complexity.

Machine-generated algorithms, proofs and software for the batch verification of digital signature schemes

As devices everywhere increasingly communicate with each other, many security applications will require low-bandwidth signatures that can be processed quickly. Pairing-based signatures can be very short, but are often costly to verify. Fortunately, they also tend to have efficient batch verification algorithms. Finding these batching algorithms by hand, however, can be tedious and error prone.We address this by presenting AutoBatch, an automated tool for generating batch verification code in either Python or C++ from a high level representation of a signature scheme. AutoBatch outputs both software and, for transparency, a LaTeX file describing the batching algorithm and arguing that it preserves the unforgeability of the original scheme.We tested AutoBatch on over a dozen pairing-based schemes to demonstrate that a computer could find competitive batching solutions in a reasonable amount of time. In particular, it found an algorithm that is faster than a batching algorithm from Eurocrypt 2010. Another novel contribution is that it handles cross-scheme batching, where it searches for a common algebraic structure between two distinct schemes and attempts to batch them together.In this work, we expand upon our paper on AutoBatch appearing in ACM CCS 2012 [in: Proceedings of the 2012 ACM Conference on Computer and Communications Security, CCS'12, ACM, New York, NY, USA, 2012, pp. 474–487] in a number of ways. We add a new loop-unrolling technique and show that it helps cut the batch verification cost of one scheme by roughly half. We describe our pruning and search algorithms in greater detail, including pseudocode and diagrams. All experiments were also re-run using the RELIC pairing library. We compare those results to our earlier results using the MIRACL library, and discuss why RELIC outperforms MIRACL in all but two cases. Automated proofs of several new batching algorithms are also included.AutoBatch is a useful tool for cryptographic designers and implementors, and to our knowledge, it is the first attempt to outsource to machines the design, proof writing and implementation of signature batch verification schemes.

Improving performance of loops on DIAM-based VLIW architectures

Recent studies show that very long instruction word (VLIW) architectures, which inherently have wide datapath (e.g. 128 or 256 bits for one VLIW instruction word), can benefit from dynamic implied addressing mode (DIAM) and can achieve lower power consumption and smaller code size with a small performance overhead. Such overhead, which is claimed to be small, is mainly caused by the execution of additionally generated special instructions for conveying information that cannot be encoded in reduced instruction bit-width. In this paper, however, we show that the performance impact of applying DIAM on VLIW architecture cannot be overlooked expecially when applications possess high level of instruction level parallelism (ILP), which is mostly the case for loops because of the result of aggressive code scheduling. We also propose a way to relieve the performance degradation especially focusing on loops since loops spend almost 90% of total execution time in programs and tend to have high ILP. We first implement the original DIAM compilation technique in a compiler, and augment it with the proposed loop optimization scheme to show that ours can clearly alleviate the performance loss caused by the excessive number of additional instructions, with the help of slightly modified hardware. Moreover, the well-known loop unrolling scheme, which would produce denser code in loops at the cost of substantial code size bloating, is integrated into our compiler. The experiment result shows that the loop unrolling technique, combined with our augmented DIAM scheme, produces far better code in terms of performance with quite an acceptable amount of code increase.

Scheduling parameter sweep workflow in the Grid based on resource competition

Workflow technology has been adopted in scientific domains to orchestrate and automate scientific processes in order to facilitate experimentation. Such scientific workflows often involve large data sets and intensive computation that necessitate the use of the Grid. To execute a scientific workflow in the Grid, tasks within the workflow are assigned to Grid resources. Thus, to ensure efficient execution of the workflow, Grid workflow scheduling is required to manage the allocation of Grid resources.Although many Grid workflow scheduling techniques exist, they are mainly designed for the execution of a single workflow. This is not the case with parameter sweep workflows, which are used for parametric study and optimisation. A parameter sweep workflow is executed numerous times with different input parameters in order to determine the effect of each parameter combination on the experiment. While executing multiple instances of a parameter sweep workflow in parallel can reduce the time required for the overall execution, this parallel execution introduces new challenges to Grid workflow scheduling. Not only is a scheduling algorithm that is able to manage multiple workflow instances required, but this algorithm also needs the ability to schedule tasks across multiple workflow instances judiciously, as tasks may require the same set of Grid resources. Without appropriate resource allocation, resource competition problem could arise.We propose a new Grid workflow scheduling technique for parameter sweep workflow called the Besom scheduling algorithm. The scheduling decision of our algorithm is based on the resource dependencies of tasks in the workflow, as well as conventional Grid resource-performance metrics. In addition, the proposed technique is extended to handle loop structures in scientific workflows without using existing loop-unrolling techniques. The Besom algorithm is evaluated using simulations with a variety of scenarios. A comparison between the simulation results of the Besom algorithm and of the three existing Grid workflow scheduling algorithms shows that the Besom algorithm is able to perform better than the existing algorithms for workflows that have complex structures and that involve overlapping resource dependencies of tasks.

Accelerating kernel density estimation on the GPU using the CUDA framework

The main problem of the kernel density estimation methods is the huge computational requirements, especially for large data sets. One way for accelerating these methods is to use the parallel processing. Recent advances in parallel processing have focused on the use Graphics Processing Units (GPUs) using Compute Unied Device Architecture (CUDA) programming model. In this work we discuss a naive and two optimised CUDA algorithms for the two kernel estimation methods: univariate and multivariate. These optimised algorithms are based on the use of shared memory tiles and loop unrolling techniques. We also present exploratory experimental results of the proposed CUDA algorithms according to the several values of parameters such as number of threads per block, tile size, loop unroll level, number of variables and data (sample) size. The experimental results show signicant performance gains of all proposed CUDA algorithms over serial CPU version and small performance speed-ups of the two optimised CUDA algorithms over naive GPU algorithms. Finally, based on extended performance results are obtained general conclusions of all proposed CUDA algorithms for some parameters.

A New Vectorization Technique for Expression Templates in C++

Vector operations play an important role in high performance computing and are typically provided by highly optimized libraries that implement the Basic Linear Algebra Subprograms (BLAS) interface. In C++ templates and operator overloading allow the implementation of these vector operations as expression templates which construct custom loops at compile time and providing a more abstract interface. Unfortunately existing expression template libraries lack the performance of fast BLAS implementations. This paper presents a new approach - Statically Accelerated Loop Templates (SALT) - to close this performance gap by combining expression templates with an aggressive loop unrolling technique. Benchmarks were conducted using the Intel C++ compiler and GNU Compiler Collection to assess the performance of our library relative to Intel's Math Kernel Library as well as the Eigen template library. The results show that the approach is able to provide optimization comparable to the fastest available BLAS implementations, while retaining the convenience and flexibility of a template library.

Computing the correct Increment of Induction Pointers with application to loop unrolling

Induction pointers (IPs) are the analogue of induction variables (IVs), namely, pointers that are advanced by a fixed amount every iteration of a loop (e.g., p = p → next → next ). Although IPs have been considered in previous works, there is no algorithm to properly compute the correct amount of pointer jumping (AOPJ) by which IPs should be advanced if loop unrolling is to be applied to loops of the form while ( p ) { … p = p → next → next ; } . The main difficulty in computing the correct AOPJ of IPs is that pointers can be used to modify the data structure that is traversed by the loop (e.g., adding/removing/by-passing elements). Consequently, a simple advancement p = p → next in a loop does not necessarily mean that p is advanced by one element every iteration. This situation contrasts with the use of IVs, which cannot change the structure of arrays that are traversed by loops. Hence, if i is an IV, A [ i + 1 ] will always mean the next element of A [ ] , while if p = p → next ; is preceded by p → next = q ; it may be advanced by k > 1 elements at every iteration. The proposed method for computing the correct AOPJ of IPs and an accompanying loop unrolling technique were implemented in the SUIF compiler for C programs. Our experiments with automatic unrolling of loops with pointers yielded an improvement of 3–5% for a set of SPEC2000 programs. Experiments with a VLIW IA-64 machine also verified the usefulness of this approach for embedded systems.

Fast multi-core based multimodal registration of 2D cross-sections and 3D datasets.

BackgroundSolving bioinformatics tasks often requires extensive computational power. Recent trends in processor architecture combine multiple cores into a single chip to improve overall performance. The Cell Broadband Engine (CBE), a heterogeneous multi-core processor, provides power-efficient and cost-effective high-performance computing. One application area is image analysis and visualisation, in particular registration of 2D cross-sections into 3D image datasets. Such techniques can be used to put different image modalities into spatial correspondence, for example, 2D images of histological cuts into morphological 3D frameworks.ResultsWe evaluate the CBE-driven PlayStation 3 as a high performance, cost-effective computing platform by adapting a multimodal alignment procedure to several characteristic hardware properties. The optimisations are based on partitioning, vectorisation, branch reducing and loop unrolling techniques with special attention to 32-bit multiplies and limited local storage on the computing units. We show how a typical image analysis and visualisation problem, the multimodal registration of 2D cross-sections and 3D datasets, benefits from the multi-core based implementation of the alignment algorithm. We discuss several CBE-based optimisation methods and compare our results to standard solutions. More information and the source code are available from http://cbe.ipk-gatersleben.de.ConclusionsThe results demonstrate that the CBE processor in a PlayStation 3 accelerates computational intensive multimodal registration, which is of great importance in biological/medical image processing. The PlayStation 3 as a low cost CBE-based platform offers an efficient option to conventional hardware to solve computational problems in image processing and bioinformatics.

Performance Evaluation of Multi-Core Intel Xeon Processors on Basic Linear Algebra Subprograms

Multi-core technology is a natural next step in delivering the benefits of Moore's law to computing platforms. On multi-core processors, the performance of many applications would be improved by parallel processing threads of codes using multi-threading techniques. This paper evaluates the performance of the multi-core Intel Xeon processors on the widely used basic linear algebra subprograms (BLAS). On two dual-core Intel Xeon processors with Hyper-Threading technology, our results show that a performance of around 20 GFLOPS is achieved on Level-3 (matrix-matrix operations) BLAS using multi-threading, SIMD, matrix blocking, and loop unrolling techniques. However, on a small size of Level-2 (matrix-vector operations) and Level-1 (vector operations) BLAS, the use of multi-threading technique speeds down the execution because of the thread creation overheads. Thus the use of Intel SIMD instruction set is the way to improve the performance of single-threaded Level-2 (6 GFLOPS) and Level-1 BLAS (3 GFLOPS). When the problem size becomes large (cannot fit in L2 cache), the performance of the four Xeon cores is less than 2 and 1 GFLOPS on Level-2 and Level-1 BLAS, respectively, even though eight threads are executed in parallel on eight logical processors.

High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Areathroughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for nonfeedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over GF(2 4 ) 2 , throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 μm CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture

In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-/spl mu/m CMOS standard cell library, and which achieves over 10-Gbps throughput in all encryption modes, including cipher block chaining (CBC) mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining and/or loop unrolling techniques cannot be applied. To reduce the propagation delays of the S-Box, the slowest function block, we developed a special circuit architecture that we call twisted-binary decision diagram (BDD), where the fanout of signals is distributed in the S-Box circuit. Our S-Box is 1.5 to 2 times faster than the conventional S-Box implementations. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is also used for an additional speedup.

High performance sparse static solver in finite element analyses with loop-unrolling

Symmetric positive definite equation solvers play a very important role in promoting the efficiency of the finite element analyses (FEA). The focus of this paper is to describe a new storage scheme—cell-sparse storage scheme—and the corresponding algorithm of the direct symmetric positive definite equation solver in FEA. Loop-unrolling (or simply unrolling) techniques are incorporated into sparse solvers to enhance the vector speed. Sparse storage schemes, out-of-core strategy, and numerical factorization are discussed. The performance in terms of elapsed time and memory requirement of different solvers are demonstrated by finding static displacement vectors for practical engineering problems. Numerical tests indicate that the cell-sparse storage scheme and the two-level unrolling can improve the performance of symmetric positive definite equation solvers significantly.

Numerical Factorization Methods for Interior Point Algorithms

Interior point algorithms for linear programming achieve significant reductions in computer time over earlier methods for many large linear programming problems (LPs) and solve problems larger than previously possible. The most computationally intensive step in each iteration of any interior point algorithm is the numerical factorization of a sparse, symmetric, positive definite matrix. In large or relatively dense problems, 80–90% or more of computational time is spent in this step. This study describes our implementations of two algorithms for performing this factorization, the column Cholesky and the multifrontal methods, based on graph theory applied to sparse symmetric matrices. We use advanced techniques such as loop unrolling and equivalent sparse matrix reordering to improve the performance of the factorization step. Our studies are incorporated into an implementation of the primal-dual barrier algorithm. Computational experiments on relatively large LPs on a DEC station 3100 demonstrate that the primal-dual barrier algorithm using our advanced column Cholesky outperforms by 20–60% the same algorithm using a straightforward column Cholesky. Also, our multifrontal method using the loop unrolling technique in a partial inner product routine shows a 10–50% speedup compared with no loop unrolling. The two methods exhibit comparable overall performance. INFORMS Journal on Computing, ISSN 1091-9856, was published as ORSA Journal on Computing from 1989 to 1995 under ISSN 0899-1499.

Vector unsymmetric eigenequation solver for nonlinear flutter analysis on high-performance computers

An efficient, vector-version generalized unsymmetric eigenequation solver is developed for large-amplitude vibration and nonlinear panel flutter analyses by finite-element methods on high-performance computers. The proposed eigensolver is designed to extract extreme eigenpairs which are all that are required in solving panel flutter problems. A loop-unrolling technique is employed to enhance the vector speed of the eigensolver. A finiteelement approach is presented for determining the nonlinear flutter characteristics of isotropic and composite panels using unsteady, third-order piston theory aerodynamics. Both nonlinear structural (large-amplitude, and nonlinear aerodynamics terms are considered in the finite-element formulation. Solution procedures are presented to solve the nonlinear panel flutter and large amplitude-free vibration finite-element equations. Nonlinear flutter analyses are performed for different dynamic pressures A; and maximum deflection-to-thickness ratios clh. Large-amplitude vibration finite-element results are compared with classical analytical solutions. Nonlinear aerodynamic and linear structural finite-element flutter results for composite panels are also presented.

Designing programming languages for the analyzability of pointer data structures

In this paper we propose a programming language mechanism and associated compiler techniques which significantly enhance the analyzability of pointer-based data structures frequently used in non-scientific programs. Our approach is based on exploiting two important properties of pointer data structures: structural inductivity and speculative traversability. Structural inductivity facilitates the application of a static interference analysis method for such pointer data structures based on path matrices, and speculative traversability is utilized by a novel loop unrolling technique for while loops that exploit fine-grain parallelism by speculatively traversing such data structures. The effectiveness of this approach is demonstrated by applying it to a collection of loops found in typical non-scientific C programs.

A parallel-vector equation solver for unsymmetric matrices on supercomputers

A parallel-vector unsymmetric equation solver is presented. The solver exploits both vector and parallel capabilities provided by modern, high-performance supercomputers. A special storage scheme and loop-unrolling technique are used to optimize the vector performance. A parallel FORTRAN language is used to develop the solver on the CRAY 2 and CRAY Y-MP multiple processing computer environment. Three numerical examples are presented which demonstrate the efficiency and accuracy of this equation solver. The first two examples demonstrate the improved performance, and the third example utilizes the proposed solver to solve a highly non-linear, unsymmetric finite element formulation for panel flutter.