Loop Nests Research Articles

Performance Impact of Nested Congestion Control on Transport-Layer Multipath Tunneling

Multipath wireless access aims to seamlessly aggregate multiple access networks to increase data rates and decrease latency. It is currently being standardized through the ATSSS architectural framework as part of the fifth-generation (5G) cellular networks. However, facilitating efficient multi-access communication in next-generation wireless networks poses several challenges due to the complex interplay between congestion control (CC) and packet scheduling. Given that enhanced ATSSS steering functions for traffic splitting advocate the utilization of multi-access tunnels using congestion-controlled multipath network protocols between user equipment and a proxy, addressing the issue of nested CC becomes imperative. In this paper, we evaluate the impact of such nested congestion control loops on throughput over multi-access tunnels using the recently introduced Multipath DCCP (MP-DCCP) tunneling framework. We evaluate different combinations of endpoint and tunnel CC algorithms, including BBR, BBRv2, CUBIC, and NewReno. Using the Cheapest Path First scheduler, we quantify and analyze the impact of the following on the performance of tunnel-based multipath: (1) the location of the multi-access proxy relative to the user; (2) the bottleneck buffer size, and (3) the choice of the congestion control algorithms. Furthermore, our findings demonstrate the superior performance of BBRv2 as a tunnel CC algorithm.

Control method based on real–imaginary decomposition at the switching frequency for multiple active bridge converters

AbstractIsolated multiple port DC/DC converters, such as the Multiple Active Bridge (MAB) converter, have many recent applications, such as interconnection between grids, isolated uninterruptible power sources (UPSs) and electric vehicle chargers. MAB converter is an attractive solution from the point of view of the hardware because of its symmetry and its capability to be extended to any number of bridges with a moderate number of components. However, the main challenge of this converter is the control method in order to achieve independent control between the different ports and to minimize recirculating currents. For that reason, three‐port power converters have been already investigated, but many improvements can be done for a larger number of ports. This paper proposes to use a Fourier decomposition for the main power signals to separate their real and imaginary parts. As the signals work at the switching frequency, this decomposition is developed with analog electronics. Based on that, a general control method for regulating the power at the different ports is presented using the first harmonic component, which delivers most of the power. In this proposal, two nested control loops ensure accuracy for the DC power flow. Simulation and experimental results validate the proposal.

Modeling the Interplay between Loop Tiling and Fusion in Optimizing Compilers Using Affine Relations

Loop tiling and fusion are two essential transformations in optimizing compilers to enhance the data locality of programs. Existing heuristics either perform loop tiling and fusion in a particular order, missing some of their profitable compositions, or execute ad-hoc implementations for domain-specific applications, calling for a generalized and systematic solution in optimizing compilers. In this article, we present a so-called basteln (an abbreviation for backward slicing of tiled loop nests) strategy in polyhedral compilation to better model the interplay between loop tiling and fusion. The basteln strategy first groups loop nests by preserving their parallelism/tilability and next performs rectangular/parallelogram tiling to the output groups that produce data consumed outside the considered program fragment. The memory footprints required by each tile are then computed, from which the upward exposed data are extracted to determine the tile shapes of the remaining fusion groups. Such a tiling mechanism can construct complex tile shapes imposed by the dependences between these groups, which are further merged by a post-tiling fusion algorithm for enhancing data locality without losing the parallelism/tilability of the output groups. The basteln strategy also takes into account the amount of redundant computations and the fusion of independent groups, exhibiting a general applicability. We integrate the basteln strategy into two optimizing compilers, with one a general-purpose optimizer and the other a domain-specific compiler for deploying deep learning models. The experiments are conducted on CPU, GPU, and a deep learning accelerator to demonstrate the effectiveness of the approach for a wide class of application domains, including deep learning, image processing, sparse matrix computation, and linear algebra. In particular, the basteln strategy achieves a mean speedup of 1.8× over cuBLAS/cuDNN and 1.1× over TVM on GPU when used to optimize deep learning models; it also outperforms PPCG and TVM by 11% and 20%, respectively, when generating code for the deep learning accelerator.

Efficient solution of bimaterial Riemann problems for compressible multi-material flow simulations

When solving compressible multi-material flow problems, an unresolved challenge is the computation of advective fluxes across material interfaces that separate drastically different thermodynamic states and relations. A popular idea in this regard is to locally construct bimaterial Riemann problems, and to apply their exact solutions in flux computation. For general equations of state, however, finding the exact solution of a Riemann problem is expensive as it requires nested loops. Multiplied by the large number of Riemann problems constructed during a simulation, the computational cost often becomes prohibitive. The work presented in this paper aims to accelerate the solution of bimaterial Riemann problems without introducing approximations or offline precomputation tasks. The basic idea is to exploit some special properties of the Riemann problem equations, and to recycle previous solutions as much as possible. Following this idea, four acceleration methods are developed, including (1) a change of integration variable through rarefaction fans, (2) storing and reusing integration trajectory data, (3) step size adaptation, and (4) constructing an R-tree on the fly to generate initial guesses. The performance of these acceleration methods is assessed using four example problems in underwater explosion, laser-induced cavitation, and hypervelocity impact. These problems exhibit strong shock waves, large interface deformation, contact of multiple (>2) interfaces, and interaction between gases and condensed matters. For all the problems, the acceleration methods are able to significantly reduce the computational cost without affecting solver robustness or solution accuracy. In different cases, the solution of bimaterial Riemann problems is accelerated by 37 to 87 times. As a result, the total cost of advective flux computation, which includes the exact Riemann problem solution at material interfaces and the numerical flux calculation over the entire computational domain, is accelerated by 18 to 81 times.

Hybrid perimeter control with real-time partitions in heterogeneous urban networks: An integration of deep learning and MPC

Network-wide perimeter control strategies have been shown promise in recent years. These perimeter control strategies are mostly based on networks with fixed boundaries. However, fixed partitions may not exploit the full potential of control performance when traffic condition dynamically changes. This study proposes a hybrid MPC-based perimeter control method to tackle traffic congestion with uneven traffic demand loading by an MPC-based perimeter control framework in which the control boundary between reservoirs is dynamically altered. The framework integrates dynamic partitions into the prediction model to formulate an optimization, in which optimal traffic performance is achieved by iteratively finding the appropriate partitions as well as the control decision variables. Moreover, a Deep Learning (DL) based estimator is incorporated into the framework to address the hefty computational burden caused by the nesting of optimization loops. In the hybrid scheme, the DL-based prediction replaces the model-based prediction if a confidence condition can be fulfilled. Comparison analysis is conducted to evaluate the necessity of perimeter control with real-time partitioning. Further results show that the hybrid scheme is effective and computationally efficient. Besides, sensitivity analysis of different confidence thresholds pinpoints the robustness of the hybrid scheme.

Execution of stored programs by a rapid single-flux-quantum random-access-memory-embedded bit-serial microprocessor using 50-GHz clock frequency

We have demonstrated the execution of several programs stored in an instruction memory by a rapid single-flux-quantum bit-serial 8-bit microprocessor named CORE e2h. We employed a minimal instruction set architecture composed of 13 instructions based on the reduced instruction set computer. We integrated a 128-bit instruction memory and a 128-bit data memory with an arithmetic logic unit, two registers, a program counter, an instruction register, and a controller unit on a single chip. The bit-serial operation was performed by an on-chip clock generator, while the system clocks are provided from room-temperature electronics. The CORE e2h was made up of 11 000 Nb/AlOx/Nb Josephson junctions and fabricated with the Advanced Industrial Science and Technology 10-kA/cm2, 9-Nb-layer process. We obtained the correct results for all the executed programs, including the integer division, the two kinds of summation algorithms, the Euclidean algorithm, and finding the greatest divisor. These test programs contained a single or nested double loop, and the maximum number of executed instructions was 205. We confirmed the stable operation with the DC bias margins of around 10% at 50-GHz for different test programs. The measured electric power consumption was 2.5 mW at 4.2 K, and the estimated computing power was 500 × 106 instructions/s.

A Parallel Tiled and Sparsified Four-Russians Algorithm for Nussinov's RNA Folding.

To enable extensive research on the ribonucleic acid (RNA) molecule, predicting its spatial structure stands as a much-valued research field. In this regard, Nussinov and Jacobson published the (now) de facto solution to predict the halfway secondary structure, which runs in cubic time for an n-nucleotide sequence. We design our contribution starting from two of the several works conducted to improve this running time. First, those of Frid and Gusfield, which associate a speedup named sparsification with an on-demand Four-Russians paradigm to achieve the fastest theoretical solution known to date. And second, those of Palkowski and Bielecki, which efficiently restructure the classical Nussinov loop nest with a novel tiling technique. Alongside other loop transformations, this paper shows that, owing to loop restructuring promoting cache reuse and variable-grained parallelism, applying the latter approach to the Frid and Gusfield doubly sped-up loop nest yields outperforming improvements both in sequential and in parallel. In fact, following empirical evaluation, we have obtained relatively to Palkowski's sequential basis, speedups up to x3.26 sequentially and up to x28.50 on 32 threads of a multicore processor with a 30,000-nucleotide sequence. Furthermore, the massive parallel environment in graphics cards has led this speedup factor to reach x44.37.

Unity Power Factor Operation in Microgrid Applications Using Fuzzy Type 2 Nested Controllers

The issue of low-power factor operation microgrids was reported for several layouts. Although numerous power factor improvement strategies have been applied and tested, various concerns remain to be addressed such as transient performance, simplicity of implementation, and satisfying the power-quality standards. The presented research aimed to design and implement controllers that can improve the transient response of microgrids due to changes in the load demand and achieve a near-unity power factor at the AC grid side, to which the DC microgrid is connected. Due to the nonlinear nature of microgrids, as they rely on power electronics converters, a Fuzzy type 2 controller was designed, implemented, and tested. The focus was given to improving the power factor of the DC microgrids. The validation of the proposed technique was verified by comparing its performance with Fuzzy type 1 and autotuned conventional PI controllers. To achieve the set aims, two nested control loops were designed with an inner current loop and an outer voltage loop. Besides MATLAB/Simulink simulations, a 10 kHz-sampling dSPACE platform was used to implement the suggested system. Two operational scenarios were tested: (1) a step change in the DC link voltage and (2) a change in the AC load (increase and decrease) at the output of the power inverter, connected to the DC grid. The simulation and experimental results confirmed that the proposed Fuzzy type 2 controller performed better than the other two techniques regarding the dynamic response, steady-state error, and compliance with power quality standards. Conventional approaches develop controllers using a linearized model, which limits the model accuracy and ignores higher-order variability. The method employs the nonlinear model. Fuzzy type 2 can better approximate high-precision problems than Fuzzy type 1.

NPDP benchmark suite for the evaluation of the effectiveness of automatic optimizing compilers

The paper presents a benchmark suite of ten non-serial polyadic dynamic programming (NPDP) kernels, which are designed to test the efficiency of tiled code generated by polyhedral optimization compilers. These kernels are mainly derived from bioinformatics algorithms, which pose a significant challenge for automatic loop nest tiling transformations. The paper describes algorithms implemented with examined kernels and unifies them in the form of loop nests presented in the C language. The purpose is to reconsider the execution and monitoring of codes, typically used in past and current publications. For carrying out experiments with introduced benchmarks, we applied the two source-to-source compilers, PLuTo and TRACO, to generate cache-efficient codes and analyzed their performance on four multi-core machines. We discuss the limitations of well-known tiling approaches and outline future tiling strategies to generate effective tiled code by means of optimizing compilers for introduced benchmarks.

Optimization of a Geophysical Application in GPU Through the Loop Tiling Technique

This work aims to present the results obtained in optimizing a viscoacoustic geophysical model written with the DEVITO tool and optimized using the OpenACC tile directive for GPU execution. We compared three versions of the operator using the NVIDIA NCU profiling tool: Naive, Tiling (32,4,4), and Mixed Tiling. The Naive version does not use the loop tiling technique, the Tiling (32,4,4) version applies a tile of dimensions (32, 4, 4), and the Mixed Tiling version uses different tile sizes to other loop nests. Analyzing the experimental results, it is notable that the optimized versions substantially increase the cache hit rates and reduce the execution time by about 50%, attesting to the validity of the proposed solutions.

Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-iteration

This article presents a code generator for sparse tensor contraction computations. It leverages a mathematical representation of loop nest computations in the sparse polyhedral framework (SPF), which extends the polyhedral model to support non-affine computations, such as those that arise in sparse tensors. SPF is extended to perform layout specification, optimization, and code generation of sparse tensor code: (1) We develop a polyhedral layout specification that decouples iteration spaces for layout and computation; and (2) we develop efficient co-iteration of sparse tensors by combining polyhedra scanning over the layout of one sparse tensor with the synthesis of code to find corresponding elements in other tensors through an SMT solver. We compare the generated code with that produced by a state-of-the-art tensor compiler, TACO. We achieve on average 1.63× faster parallel performance than TACO on sparse-sparse co-iteration and describe how to improve that to 2.72× average speedup by switching the find algorithms. We also demonstrate that decoupling iteration spaces of layout and computation enables additional layout and computation combinations to be supported.

Program representations for predictive compilation: State of affairs in the early 20’s

In the last five years, predictive compilation has advanced with long strides. Contributions in the field include new program embeddings, new learning architectures, and datasets with millions of programs. This paper evaluates 25 state-of-the-art program embeddings, three of them new, plus two learning models from previous work. We have trained this apparatus with three large datasets, and have applied it onto three classification problems. When classifying programs according to the problem that they solve, we reproduced the high-accuracy results seen in previous work. However, we have not been able to repeat these results in the two new classification challenges that we study: namely, determining the depth of the most nested loop in a program and determining the best sequence of optimizations to reduce code size of programs. Negative results emerged, even in spite of the large number of classifiers, 25, that we have evaluated. Surprisingly, using the histogram of instruction opcodes, a very simple program embedding, led to about the same classification accuracy than embeddings like Ir2Vec or Inst2Vec , which were designed to solve stochastic compilation tasks.

Thermofluids performances on innovative design with multi-circuit nested loop applicable for double-layer microchannel heat sinks

This study numerically proposes a novel microchannel heat sink design named multi-circuit nested loop (ML) to strength the thermal performance of double-layer microchannel heat sinks (DMCHS). The ML is introduced into the DMCHS to enhance the thermal characteristics and is compared with the traditional straight DMCHS. Due to the complexity of the ML-DMCHS, 4 different working conditions on inlets and outlets are designed to find the optimal one. Based on the analysis of the thermal gradients on substrate, flow characteristics of coolant, overall thermal resistance and thermal performance factor, it is found that the novel ML-DMCHS not only can significantly reduce the peak temperature, but also offer better temperature uniformity on substrate. The peak temperature on substrate can be reduced up to 34 K when compared with traditional parallel straight double-layer microchannels (P-DMCHS). Furthermore, the inner cooling circuit in ML-DMCHS shows greater impact on the lowest temperature on substrate, while the outer cooling circuit affects more on the peak temperature.

UniRec: a unimodular-like framework for nested recursions and loops

Scheduling transformations reorder operations in a program to improve locality and/or parallelism. There are mature loop transformation frameworks such as the polyhedral model for composing and applying instance-wise scheduling transformations for loop nests.In recent years, there have been efforts to build frameworks for composing and applying scheduling transformations for nested recursion and loops, but these frameworks cannot employ the full power of transformations for loop nests since they have overly-restrictive representations. This paper describes a new framework, UniRec, that not only generalizes prior frameworks for reasoning about transformations on recursion, but also generalizes the unimodular framework, and hence unifies reasoning about perfectly-nested loops and recursion.

Hybrid MPI and CUDA paralleled finite volume unstructured CFD simulations on a multi-GPU system

Porting unstructured Computational Fluid Dynamics (CFD) analysis of compressible flow to Graphics Processing Units (GPUs) confronts two difficulties. Firstly, non-coalescing access to the GPU’s global memory is induced by indirect data access leading to performance loss. Secondly, data exchange among multi-GPU is complex due to data communication between processes and transfer between host and device, which degrades scalability. For increasing data locality on unstructured finite volume GPU simulations for compressible flow, we perform some optimizations, including cell and face renumbering, data dependence resolving, nested loops split, and loop mode adjustment. Then, a hybrid MPI-CUDA parallel framework with packing and unpacking exchange data on GPU is established for multi-GPU computing. Finally, after optimizations, the performance of the whole application on a GPU is increased by around 50%. Simulations of ONERA M6 cases on a single GPU (Nvidia Tesla V100) can achieve an average of 13.4 speedup compared to those on 28 CPU cores (Intel Xeon Gold 6132). On the baseline of 2 GPUs, strong scaling results show a parallel efficiency of 42% on 200 GPUs, while weak scaling tests give a parallel efficiency of 82.4% up to 200 GPUs.

3D Tiled Code Generation for Nussinov’s Algorithm

Current state-of-the-art parallel codes used to calculate the maximum number of pairs for a given RNA sequence by means of Nussinov’s algorithm do not allow for achieving speedup close up to the number of the processors used for execution of those codes on multi-core computers. This is due to the fact that known codes do not make full use of and derive benefit from cache memory of such computers. There is a need to develop new approaches allowing for increasing cache exploitation in multi-core computers. One of such possibilities is increasing the dimension of tiles in generated target tiled code and assuring a similar size of generated tiles. The article presents an approach allowing us to produce 3D parallel code with tiling calculating Nussinov’s RNA folding, i.e., code with the maximal tile dimension possible for the loop nest, executing Nussinov’s algorithm. The approach guarantees that generated tiles are of a similar size. The code generated with the presented approach is characterized by increased code locality and outperforms all closely related ones examined by us. This allows us to considerably reduce execution time required for computing the maximum number of pairs of any nested structure for larger RNA sequences by means of Nussinov’s algorithm.

Power quality enhancement through ancillary services provided by power electronic converters

Modern electrical power grids are susceptible to several problems in terms of power quality due to the integration of renewable energy sources, the connection of nonlinear loads, and power electronics-based devices. In this sense, this work proposes a novel nonlinear control scheme that allows, through the use of a power electronic converter, to provide ancillary services to the electrical power grid, intending to achieve three different control objectives: voltage regulation, harmonic distortion compensation, and the power factor correction at a power system node, depending on the end-user requirements, and by doing so enhance the power quality. The proposed control scheme uses nested control loops based on super-twisting sliding modes, nonlinear optimal tracking control, and a fast-convergent harmonic estimator with a decentralized structure. Simulation results validate the effectiveness of our proposed scheme.

Synergistic flame retardant weft-knitted alginate/viscose fabrics with MXene coating for multifunctional wearable heaters

Flexible wearable heaters have received increasing attention in energy-saving, diverse personal thermal requirements, and healthcare management. Herein, considering the fire safety application of wearable heaters, the biodegradable alginate fibers and flame retardant (FR) viscose fibers are attempted to mix and weft-knit into the fabric, which interestingly exhibits synergetic flame retardancy with low afterflame time, afterglow time, and peak heat release rate. Further, assisted by the highly conductive Ti3C2Tx (MXene) nanosheets on the surface of the fabric and the periodic nested loops of the knitted fabric, the integrated fabrics possess excellent electrical performance (2Ω sq−1) with the MXene content of 9.13 wt%, electromagnetic interference (EMI) shielding efficiency of 55 dB in the X band, preferable Joule heating performance under safe low voltage (123 °C at 3.5 V) and sunlight/far-infrared heating performance. The superior flame retardancy and multifunctional properties arose from the high-temperature induced well-constructed char layer, unique functionality of interconnected MXene network and multiple scattering of light or wave. Combined with the superior flame retardancy and multifunctional properties, the weft-knitted alginate/FR viscose fabrics with MXene coating become the ideal candidate materials in the fields of wearable heaters with high safety.

Data distribution and parallel code generation for heterogeneous computational clusters

We present new techniques for compilation of sequential programs for almost affine accesses in loop nests for distributed-memory parallel architectures. Our approach is implemented as a source-to-source automatic parallelizing compiler that expresses parallelism with the DVMH directive-based programming model. Compared to all previous approaches ours addresses all three main sub-problems of the problem of distributed memory parallelization: data and computation distribution and communication optimization. Parallelization of sequential programs with structured grid computations is considered. In this paper, we use the NAS Parallel Benchmarks to evaluate the performance of generated programs and provide experimental results on up to 9 nodes of a computational cluster with two 8-core processors in a node.

Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators

A spatial accelerator’s efficiency depends heavily on both its mapper and cost models to generate optimized mappings for various operators of DNN models. However, existing cost models lack a formal boundary over their input programs (operators) for accurate and tractable cost analysis of the mappings, and this results in adaptability challenges to the cost models for new operators. We consider the recently introduced Maestro Data-Centric (MDC) notation and its analytical cost model to address this challenge because any mapping expressed in the notation is precisely analyzable using the MDC’s cost model. In this article, we characterize the set of input operators and their mappings expressed in the MDC notation by introducing a set of conformability rules . The outcome of these rules is that any loop nest that is perfectly nested with affine tensor subscripts and without conditionals is conformable to the MDC notation. A majority of the primitive operators in deep learning are such loop nests. In addition, our rules enable us to automatically translate a mapping expressed in the loop nest form to MDC notation and use the MDC’s cost model to guide upstream mappers. Our conformability rules over the input operators result in a structured mapping space of the operators, which enables us to introduce a mapper based on our decoupled off-chip/on-chip approach to accelerate mapping space exploration. Our mapper decomposes the original higher-dimensional mapping space of operators into two lower-dimensional off-chip and on-chip subspaces and then optimizes the off-chip subspace followed by the on-chip subspace. We implemented our overall approach in a tool called Marvel , and a benefit of our approach is that it applies to any operator conformable with the MDC notation. We evaluated Marvel over major DNN operators and compared it with past optimizers.