Loop Nests Research Articles

Specification Guided Automated Synthesis of Feedback Controllers

The growing use of complex Cyber-Physical Systems (CPSs) in safety-critical applications has led to the demand for the automatic synthesis of robust feedback controllers that satisfy a given set of formal specifications. Controller synthesis from the high-level specification is an NP-Hard problem. We propose a heuristic-based automated technique that synthesizes feedback controllers guided by Signal Temporal Logic (STL) specifications. Our technique involves rigorous analysis of the traces generated by the closed-loop system, matrix decomposition, and an incremental multi-parameter tuning procedure. In case a controller cannot be found to satisfy all the specifications, we propose a technique for modifying the unsatisfiable specifications so that the controller synthesized for the satisfiable subset of specifications now also satisfies the modified specifications. We demonstrate our technique on eleven controllers used as standard closed-loop control system benchmarks, including complex controllers having multiple independent or nested control loops. Our experimental results establish that the proposed algorithm can automatically solve complex feedback controller synthesis problems within a few minutes.

Space-Time Loop Tiling for Dynamic Programming Codes

We present a new space-time loop tiling approach and demonstrate its application for the generation of parallel tiled code of enhanced locality for three dynamic programming algorithms. The technique envisages that, for each loop nest statement, sub-spaces are first generated so that the intersection of them results in space tiles. Space tiles can be enumerated in lexicographical order or in parallel by using the wave-front technique. Then, within each space tile, time slices are formed, which are enumerated in lexicographical order. Target tiles are represented with multiple time slices within each space tile. We explain the basic idea of space-time loop tiling and then illustrate it by means of an example. Then, we present a formal algorithm and prove its correctness. The algorithm is implemented in the publicly available TRACO compiler. Experimental results demonstrate that parallel codes generated by means of the presented approach outperform closely related manually generated ones or those generated by using affine transformations. The main advantage of code generated by means of the presented approach is its enhanced locality due to splitting each larger space tile into multiple smaller tiles represented with time slices.

A CPW-fed rectangular nested loop antenna for penta band wireless applications

A miniaturized coplanar waveguide (CPW) fed rectangular nested loop antenna is proposed for penta band wireless applications. Multiband and antenna compactness are obtained by using rectangular loop resonators. The proposed antenna has been optimized by increasing the number of loop iterations. The designed antenna comprises four rectangular loops, it constructs the antenna to excite 1.01 GHz, 1.67 GHz, 2.30 GHz, 2.92 GHz and 3.48 GHz frequency bands. The fabricated geometry has a dimension of 30 × 30 × 1.6 mm3, which is developed on a low-cost Flame Retardant-4 substrate having εr = 4.4 and tanδ = 0.02. The resonance behavior of the proposed antenna is verified by employing LC quasi-static design equations. The measured reflection coefficient and far-field pattern are exhibited to support the performance of the designed antenna for wireless applications.

A pragmatic controller for a gantry crane

A gantry crane presents a control problem with ten state variables. The undamped swinging of the load has led earlier researchers to apply cumbersome control strategies. The essence of pragmatic control is gleaned from autopilot designs of half a century ago. The control is designed as a set of ‘nested loops’, where the innermost loop takes the form of a velocity loop wrapped around a motor to give crisp velocity control. Target values are derived from states in the outer loops, to be applied to a succession of inner loops. These target values are subjected to constraints. Thus in the case of the crane, the horizontal position of the load can be considered to be the two outermost variables. In this study, from the load position error, two target velocity components are calculated and subjected to limits. The velocity error leads in turn to a target acceleration of the load and subsequently, to the target displacement that takes place between the horizontal coordinates of the hoist and the load. In this paper, the pragmatic control technique is demonstrated with the aid of a JavaScript and MATLAB software programs using a state-space model.

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores

Single-issue processor cores are very energy efficient but suffer from the von Neumann bottleneck, in that they must explicitly fetch and issue the loads/storse necessary to feed their ALU/FPU. Each instruction spent on moving data is a cycle not spent on computation, limiting ALU/FPU utilization to 33 percent on reductions. We propose “Stream Semantic Registers” to boost utilization and increase energy efficiency. SSR is a lightweight, non-invasive RISC-V ISA extension which implicitly encodes memory accesses as register reads/writes, eliminating a large number of loads/stores. We implement the proposed extension in the RTL of an existing multi-core cluster and synthesize the design for a modern 22 nm technology. Our extension provides a significant, 2x to 5x, architectural speedup across different kernels at a small 11 percent increase in core area. Sequential code runs 3x faster on a single core, and 3x fewer cores are needed in a cluster to achieve the same performance. The utilization increase to almost 100 percent in leads to a 2x energy efficiency improvement in a multi-core cluster. The extension reduces instruction fetches by up to 3.5x and instruction cache power consumption by up to 5.6x. Compilers can automatically map loop nests to SSRs, making the changes transparent to the programmer.

Real-Time Voltage Control Based on a Cascaded Super Twisting Algorithm Structure for DC–DC Converters

This article proposes a second-order sliding mode control law, based on a super twisting algorithm (STA), aimed at regulating the output voltage of a dc–dc buck converter. A closed-loop system is designed consisting of two distinct nested loops organized within a cascaded STA structure. Several sliding mode control algorithms are here surveyed for the regulation of a dc–dc buck converter. The STA of second-order sliding mode is also experimented in an HIL system. The comparative evaluations include comparing the output voltage transient responses to load step changes for all developed sliding mode control algorithms and the start-up responses of the output voltage to step changes of the input voltage of the buck converter. Furthermore, theoretical considerations, numerical simulations, and experimental results from a laboratory prototype are compared, at different operating points, for all surveyed control methods. It results from the simulations and experiments that the designed STA achieves the fastest convergence, a consistent chattering reduction, the smallest settling time under loaded situations, and small steady-state error during load changes over all contrasted control methods.

Verified code generation for the polyhedral model

The polyhedral model is a high-level intermediate representation for loop nests that supports elegantly a great many loop optimizations. In a compiler, after polyhedral loop optimizations have been performed, it is necessary and difficult to regenerate sequential or parallel loop nests before continuing compilation. This paper reports on the formalization and proof of semantic preservation of such a code generator that produces sequential code from a polyhedral representation. The formalization and proofs are mechanized using the Coq proof assistant.

An Effective Fusion and Tile Size Model for PolyMage

Effective models for fusion of loop nests continue to remain a challenge in both general-purpose and domain-specific language (DSL) compilers. The difficulty often arises from the combinatorial explosion of grouping choices and their interaction with parallelism and locality. This article presents a new fusion algorithm for high-performance domain-specific compilers for image processing pipelines. The fusion algorithm is driven by dynamic programming and explores spaces of fusion possibilities not covered by previous approaches, and it is also driven by a cost function more concrete and precise in capturing optimization criteria than prior approaches. The fusion model is particularly tailored to the transformation and optimization sequence applied by PolyMage and Halide, two recent DSLs for image processing pipelines. Our model-driven technique when implemented in PolyMage provides significant improvements (up to 4.32×) over PolyMage’s approach (which uses auto-tuning to aid its model) and over Halide’s automatic approach (by up to 2.46×) on two state-of-the-art shared-memory multicore architectures.

AutoParallel: Automatic parallelisation and distributed execution of affine loop nests in Python

The last improvements in programming languages and models have focused on simplicity and abstraction; leading Python to the top of the list of the programming languages. However, there is still room for improvement when preventing users from dealing directly with distributed and parallel computing issues. This paper proposes and evaluates AutoParallel, a Python module to automatically find an appropriate task-based parallelisation of affine loop nests and execute them in parallel in a distributed computing infrastructure. It is based on sequential programming and contains one single annotation (in the form of a Python decorator) so that anyone with intermediate-level programming skills can scale up an application to hundreds of cores. The evaluation demonstrates that AutoParallel goes one step further in easing the development of distributed applications. On the one hand, the programmability evaluation highlights the benefits of using a single Python decorator instead of manually annotating each task and its parameters or, even worse, having to develop the parallel code explicitly (e.g., using OpenMP, MPI). On the other hand, the performance evaluation demonstrates that AutoParallel is capable of automatically generating task-based workflows from sequential Python code while achieving the same performances than manually taskified versions of established state-of-the-art algorithms (i.e., Cholesky, LU, and QR decompositions). Finally, AutoParallel is also capable of automatically building data blocks to increase the tasks’ granularity; freeing the user from creating the data chunks, and re-designing the algorithm. For advanced users, we believe that this feature can be useful as a baseline to design blocked algorithms.

Coupled circuit analysis of the brushless doubly fed machine using the winding function theory

The brushless doubly fed induction machine (BDFM) is considered as an alternative to doubly fed induction generators (DFIGs) in wind energy conversion systems. However, BDFMs have a complex machine structure, and their operations are relatively complicated. In this study, the winding function theory is used in the development of a coupled circuit (CC) model for BDFMs with nested loop (NL) and cage+NL rotors, in order to give a robust representation of the electrical operations of BDFMs. The electrical circuit analysis of BDFMs having NL and cage+NL rotors is comprehensively detailed, with the stator and rotor inductances calculated using their winding functions. The interactions of BDFM rotor loops with stator windings are demonstrated in terms of mutual inductances. CC models of different BDFMs are simulated for synchronous doubly fed BDFM operations with an emphasis on generating regions. Also, fresh insight into the torque production in BDFMs is provided, with the rotor loops and stator winding contributions to torque magnitude and ripple examined.

Position Control of a Maglev System Fed by a DC/DC Buck Power Electronic Converter

In this paper, we solve the problem of position regulation in a magnetic levitation system that is fed by a DC/DC Buck power electronic converter as a power amplifier. We present a formal asymptotic stability proof. Although this result is local, the merit of our proposal relies on the fact that this is the first time that such a control problem is solved for a magnetic levitation system, a nonlinear electromechanical plant. In this respect, we stress that most works in the literature on control of electromechanical systems actuated by power electronic converters are devoted to control brushed DC motors which are well known to have a linear model. Furthermore, despite the plant that we control in the present paper is complex, our control law is simple. It is composed by four nested loops driven by one sliding mode controller, two proportional-integral controllers, and a nonlinear proportional-integral-derivative position controller. Each one of these loops is devoted to control each one of the subsystems that compose the plant: electric current through the converter inductor, voltage at the converter capacitor, electric current through the electromagnet, and position of the ball. Thus, our proposal is consistent with the simple and intuitive idea of controlling each subsystem of the plant in order to render robust the control scheme. We stress that such a solution is complicated to derive using other control approaches such as differential flatness or backstepping. In this respect, our proposal relies on a novel passivity-based approach which, by exploiting the natural energy exchange between the mechanical and electrical dynamics, renders possible the design of a control scheme with the above cited features.

Pure Functions in C: A Small Keyword for Automatic Parallelization

The need for parallel task execution has been steadily growing in recent years since manufacturers mainly improve processor performance by increasing the number of installed cores instead of scaling the processor’s frequency. To make use of this potential, an essential technique to increase the parallelism of a program is to parallelize loops. Several automatic loop nest parallelizers have been developed in the past such as PluTo. The main restriction of these tools is that the loops must be statically analyzable which, among other things, disallows function calls within the loops. In this article, we present a seemingly simple extension to the C programming language which marks functions without side-effects. These functions can then basically be ignored when the automatic parallelizer checks the parallelizability of loops. We integrated the approach into the GCC compiler toolchain and evaluated it by running several real-world applications. Our experiments show that the C extension helps to identify additional parallelization opportunities and, thus, to significantly increase the performance of applications.

Reconstruction of Multi-Dimensional Form of Linearized Accesses to Arrays in SAPFOR

The system for automated parallelization SAPFOR (System FOR Automated Parallelization) includes tools for program analysis and transformation. The main goal of the system is to reduce the complexity of program parallelization. SAPFOR system is focused on the investigation of multilingual applications in Fortran and C programming languages. The low-level LLVM IR representation is used in SAPFOR for program analysis. This representation allows us to perform various IR-level optimizations to improve the quality of program analysis. At the same time, it loses some features of the program, which are available in its higher level representation. One of these features is the multi-dimensional structure of the arrays. Data dependence analysis is one of the main problems which should be solved to automate program parallelization. Moreover, such an analysis belongs to the class of NP-hard problems. Knowledge of the multidimensional structure of arrays allows in many cases to take into account the structure of index expressions in calls to arrays and reduce the complexity of the analysis. In addition, the use of multi-dimensional arrays allows us to use multi-dimensional processor matrix and to parallelize a whole loop nests, rather than a single loop in the nest. So, parallelism of a program is going to be increased. These opportunities are natively supported in the DVM system. This paper discusses the approach used in the SAPFOR system to recover the form of multi-dimensional arrays by their linearized representation in LLVM IR. The proposed approach has been successfully evaluated on various applications including performance tests from the NAS Parallel Benchmarks suite.

Nested control loop design for differential boost inverter using generalized averaged model in photovoltaic applications

AbstractTo use photovoltaic energy, voltage source inverters are playing an important role. The most of local AC loads such as AC motors need higher voltage than solar panel output voltage. Differential boost inverter produces an AC voltage that is greater than the DC input voltage in a single power stage. This inverter consists of two DC‐DC bilateral boost converters in which work via time‐variant duty cycles to produce sinusoidal voltage, and this feature causes complexity in control design. To deal with this complexity, new modeling so‐called generalized averaged model is used to achieve a linear time‐invariant model. In this paper, a nested control loop is designed. This control strategy consists of two control loops in which the inner loop is designed by linear quadratic regulator theory to displace poles in proper location and the second loop uses a PI‐PR controller to track desired voltage and reject disturbances. To evaluate the proposed control method, the sliding mode controller is applied and compared as well. As shown by simulations, the proposed control strategy has more reliable performance and provides higher robustness in comparison with sliding mode control technique in rigid situations such as dealing with nonlinear load, parameters values changes, and external disturbances.

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches

Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (LRU, locked, ACDC, etc.). In this article, we analyze data reuse (in the worst case) as a property of the program, and thus independent of the data cache. Our analysis method uses Abstract Interpretation on the compiled program to extract, for each static load/store instruction, a linear expression for the address pattern of its data accesses, according to the Loop Nest Data Reuse Theory. Each data access expression is compared to that of prior (dominant) memory instructions to verify whether it presents a guaranteed reuse. Our proposal manages references to scalars, arrays, and non-linear accesses, provides both temporal and spatial reuse information, and does not require the exploration of explicit data access sequences. As a proof of concept we analyze the TACLeBench benchmark suite, showing that most loads/stores present data reuse, and how compiler optimizations affect it. Using a simple hit/miss estimation on our reuse results, the time devoted to data accesses in the worst case is reduced to 27% compared to an always-miss system, equivalent to a data hit ratio of 81%. With compiler optimization, such time is reduced to 6.5%.

Parallel tiled cache and energy efficient codes for [formula omitted] RNA folding algorithms

In this paper, we consider two O(n4) RNA folding algorithms, Zuker’s recurrence and the maximum expected accuracy prediction (MEA), which are challenging dynamic programming tasks to optimize because they are computationally intensive and have a large number of non-uniform dependences. We apply our previously published approach to automatically tile and parallelize each loop in the studied algorithms by means of the polyhedral model. First, for each loop nest statement, rectangular tiles are formed within the iteration space of the loop nest. Then, those tiles are corrected to honor all dependences exposed for the original loop nest. Correction is based on applying the exact transitive closure of a dependence graph. We implemented our approach as a part of the source-to-source TRACO compiler, generated target code, and compare the performance and energy consumption of generated code with those of code obtained with the state-of-the-art PluTo compiler based on the affine transformation framework as well as with those of code generated by means of the manual cache-efficient Transpose method. Experiments were carried out on a modern multi-core processor to achieve the significant locality improvement and energy saving for generated code.

Complete implementation of the combined TEG-TEC temperature control and energy harvesting system

Previously, the combined thermoelectric generator and cooler (TEG-TEC) control technique was proposed for thermal management of devices, where the TEG mode is used for energy harvesting and the TEC mode is used for active temperature control. This research significantly improves the TEG-TEC control technique by including the components that ensure the TEG output power can truly be returned to the original power source. Specifically, two cascaded boost converters are adopted in the TEG power circuit where the former is used to achieve maximum power point tracking, and the latter provides an additional constant voltage gain to improve the circuit’s compatibility. Both a Simscape based simulation model and the modified experimental platform involving a lithium ion battery is used to demonstrate the improved implementation. Moreover, for the sake of demonstration, two control algorithms, namely the basic nested IF loop and a fuzzy logic controller, are adopted and their performances are compared. Finally, a steady state analysis of the Simscape model involving a parametric sweep of the input waste heat shows that the TEG mode can only be engaged for a certain range.

DMazeRunner

Dataflow accelerators feature simplicity, programmability, and energy-efficiency and are visualized as a promising architecture for accelerating perfectly nested loops that dominate several important applications, including image and media processing and deep learning. Although numerous accelerator designs are being proposed, how to discover the most efficient way to execute the perfectly nested loop of an application onto computational and memory resources of a given dataflow accelerator ( execution method ) remains an essential and yet unsolved challenge. In this paper, we propose dMazeRunner -- to efficiently and accurately explore the vast space of the different ways to spatiotemporally execute a perfectly nested loop on dataflow accelerators (execution methods). The novelty of dMazeRunner framework is in: i) a holistic representation of the loop nests, that can succinctly capture the various execution methods, ii) accurate energy and performance models that explicitly capture the computation and communication patterns, data movement, and data buffering of the different execution methods, and iii) drastic pruning of the vast search space by discarding invalid solutions and the solutions that lead to the same cost. Our experiments on various convolution layers (perfectly nested loops) of popular deep learning applications demonstrate that the solutions discovered by dMazeRunner are on average 9.16× better in Energy-Delay-Product (EDP) and 5.83× better in execution time, as compared to prior approaches. With additional pruning heuristics, dMazeRunner reduces the search time from days to seconds with a mere 2.56% increase in EDP, as compared to the optimal solution.

Groundwater quality evaluation using a classification model: a case study of Jilin City, China

Using the MATLAB™ platform, groundwater quality in Jilin, China, is evaluated by employing integrated- and automation-type models. Genetic algorithm (GA), particle swarm optimisation, and support vector machine (SVM) theory are coupled in the model to form two-layer loop nesting. By using a GA, the surrounding loop enters the inner loop by choosing some factors from all measured evaluation factors. The inner loop is mainly composed of the SVM model. The inner loop feeds back the fitness function value of the GA obtained by weighting the model classification accuracy, and the reduced dimensions of each evaluation factor, to the surrounding loop. This aims to adjust the direction of evolution of the GA and eliminate evaluation factors with redundant, or sparse, information. The established model is applied to evaluate groundwater quality in Jilin and reduces 16 original evaluation factors to nine through a dimensionality reduction method. The training and verification sets constructed in the model exhibit more than 95% accuracy. Among the 183 wells used for monitoring groundwater in Jilin, the numbers of I-, II-, III-, IV-, and V-type monitoring wells are two, 96, 61, 20, and four, respectively. Compared with ordinary methods of evaluating water quality, the method integrates data selection and data processing instead of performing it in two successive substeps. The method exhibits the significant effect of dimensionality reduction on the number of its evaluation factors and also shows accurate evaluation results for water quality samples. Moreover, the method’s ability to be applied in many conditions provides a good basis for its use in various classification problems including water quality evaluation.

Assessment of the prevalence of Theileria lestoquardi in sheep from the Sudan using serological and molecular methods

Malignant theileriosis of sheep and goats caused by Theileria lestoquardi is considered to be among the most important tick borne diseases in the Sudan. Information on the prevalence of the disease in different parts of the Sudan is limited. The purpose of this study was to estimate the prevalence of the disease in five states of the Sudan using molecular and serological assays. A total of 393 blood and serum samples from clinically asymptomatic sheep were analysed using nested reverse line blot (nRLB) and loop mediated isothermal amplification (LAMP), as well as an enzyme-linked immunosorbent assay (ELISA). The results indicated a sero-prevalence of 33.8% while RLB and LAMP assays revealed molecular prevalences of 29.5 and 22.6% respectively. The prevalence of Theileria lestoquardi varied significantly according to the geographical origin of the infected animals, whereas age and gender did not have a significant effect. RLB data indicated that T. lestoquardi usually occurred as a co-infection with the non-pathogenic Theileria ovis. Using RLB as a gold standard, a sensitivity of 68.1% and a specificity of 96.4% were recorded for LAMP and a sensitivity of 75.9% and a specificity of 83.8% for ELISA. The Kappa coefficient between nRLB and LAMP indicated a significant level of agreement (0.692), but only moderate concordance (0.572) between nRLB and ELISA. The results of the present study confirm and extend earlier findings regarding the widespread of T. lestoquardi infections in sheep in the Sudan. The data provide evidence that should enable the veterinary authorities to deploy appropriate control measures.