Loop Filter Research Articles

Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC.

A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio.

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter's sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively.

Full-speed domain position sensorless control strategy for PMSM based on a novel phase-locked loop

This paper proposes a full-speed-domain position-sensor-less control strategy for precise control under forward and reverse rotation conditions to address the weak convex polarity of surface-mounted permanent magnet synchronous motor (SPMSM). The strategy comprises several key stages: pre-positioning of the rotor, constant current variable frequency (I/F) start-up, construct the Luenberger State Observer, and utilization of an improved phase-locked loop (PLL) for position estimation. In the pre-positioning stage, a constant amplitude current is applied to drag the rotor to a predetermined position. Subsequently, the I/F start-up stage accelerates the motor to a predetermined speed before transitioning to the Luenberger observer for closed-loop speed control, which is based on an extended back electromotive force (back-EMF) a two-phase rotating coordinate system. The improved PLL for position and speed estimation features three components: a phase discriminator (PD), a voltage-controlled oscillator (VCO), and loop filter (LF). Experimental results demonstrate the efficacy of the proposed strategy, showing quick start-up response, speed estimation error below 2 RPM, rotor position estimation error under 0.6 degrees post-loop closure, stable tracking during rapid speed changes, and consistent accuracy and stability even under reverse rotation conditions, thereby meeting the control strategy’s objectives.

Intelligent mitigation of GPS spoofing using the Kalman filter in the tracking loop based on multi-correlator

In the last decade, spoofing attack has been known as the most dangerous intentional interference in Global Positioning System (GPS). This work suggested an algorithm that performs spoofing mitigation by utilising the Kalman filter. In particular, first, in the tracking stage multi-correlator structure is established and correlators output are investigated by using a Multi-Layer Perceptron Neural Network (MLP NN) in other to detect the spoofing attack, after that, the Kalman filter estimates the DLL discriminator output. The proposed method was verified using three different spoofing in which, the mitigation rate was 84.25%, 93.20% and 97.24%, respectively.

A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD

A dual-loop CDR (Clock and Data Recovery) is presented to recover digital data from 1 to 6.5 Gbps. The presented frequency acquisition technique is based on full rate clock architecture. By utilizing modified Digital Quadri-correlator Frequency Detector (DQFD) and Frequency Increment/Decrement Control circuit, the lock-in range is improved. Furthermore, the issue of state loss during wide frequency range detection is successfully mitigated. The inclusion of two control wires in the Coarse-fine Tuning VCO enables the utilization of separate loop filters in the dual loops, resulting in a more effective reduction of noise and jitter. Utilizing a 40-nm CMOS process, the presented CDR design has been implemented. The post-layout simulation results at 6.5 Gbps shows a P2P and root-mean-square jitter values are 17.1 ps and 5.79 ps, respectively, for the retimed data.

Periodic spiking pulse formation in broadband nonlinear optoelectronic oscillator

An approach to generating periodic spiking pulses in a broadband opto-electronic oscillator (OEO) without external injection is proposed and demonstrated. Through biasing the electro-optic Mach-Zehnder modulator (MZM) in the OEO cavity at its nonlinear working point, spiking pulses are excited by the self-generated chaos under the combined action of the loop filter response time and the nonlinear excitation effect. An interaction force is introduced between pulses. As a result, the pulse number in a single roundtrip duration and the temporal distribution of the generated spiking pulses can be tuned by adjusting the loop gain and the direct-current (DC) bias voltage of the MZM. Both numerical simulation and experiment are carried out to demonstrate the spiking pulse generation mechanism, where ultra-short spiking pulse trains with even and uneven temporal distribution are generated.

An adaptive gain phase‐locked loop for position sensorless control of permanent magnet synchronous motor drives

AbstractIn view of the cost and reliability issues caused by mechanical position sensors, position sensorless control (PSC) of permanent magnet synchronous motors (PMSMs) has received widespread attention. A series of rotor position estimation (RPE) schemes have been developed, in which the phase‐locked loop (PLL) plays an important role. However, the conventional phase‐locked loops face two thorny issues, one is the degradation of RPE performance under motor acceleration and deceleration conditions, and the other is high noise sensitivity. To this end, an adaptive gain PLL (AG‐PLL) is proposed for PSC of PMSM drives. The gains of the loop filter in the proposed AG‐PLL are adaptively adjusted with the estimation error in order to find a compromise between the estimation performance under motor acceleration and deceleration conditions and the noise sensitivity. Moreover, the proposed scheme avoids increasing the order of the PLL, so its dynamic performance is also guaranteed. The proposed scheme is tested based on the hardware‐in‐the‐loop platform.

A Low Power PLL with 1-V Supply Voltage and Two-Stage Ring Oscillator in 180-nm CMOS

This paper proposes a low-power charge pump PLL (CPPLL) with 1-V supply voltage in 180-nm CMOS technology, which serves as a low-cost clock generator for heterogeneous integration. Tradeoffs between power consumption, jitter performance and limited loop bandwidth in the conventional CPPLL have been analyzed first, followed by the explanations on reference spur issues in wide bandwidth architectures. A novel two-stage ring oscillator with low voltage capability and linear control gain has been proposed and analyzed in detail, which facilitates the implementation of this 1-V design. Fabricated in SMIC 180-nm technology, the designed PLL occupies a die area of 0.177[Formula: see text]mm2 with an integrated loop filter. The PLL draws 1.8[Formula: see text]mA when working at 480[Formula: see text]MHz, and shows a rms jitter of 7.2[Formula: see text]pS, which is 20 times more power efficient compared with PLLs with similar frequency and technology node. The design shows potential for heterogeneous integration.

Simulation and Arduino Hardware Implementation of ACO, PSO, and FPA Optimization Algorithms for Speed Control of a DC Motor

This article proposes implementing and comparing the effectiveness of three optimization algorithms (ACO, PSO, and FPA) for tuning a proportional-integral-derivative (PID) controller on an Arduino Mega 2560 board. This relatively unexplored approach aims to evaluate these algorithms through practical experiments. The choice of PID control is due to its design simplicity and widespread industrial use. Similarly, the permanent magnet DC motor (PMDC) was selected because of its crucial role in various industrial sectors. Tuning PID parameters using optimization algorithms has garnered increasing interest due to its demonstrated efficiency. Several studies have validated the stability of ACO, PSO, and FPA algorithms, justifying their selection. In this article, simulation results showed that ACO, with a response time of 0.322s and an overshoot of 0.68%, was more effective than PSO, which had a response time of 0.768s and an overshoot of 13%. FPA had a response time of 0.347s, close to ACO, but a higher overshoot of 6%. In practice, several factors come into play, such as speed ripples caused by the speed sensor, and machine saturation, which must be considered to ensure practical implementation. After adjusting the PID parameters and integrating a low-pass filter in the feedback loop, ACO, with a response time of 0.596s and an overshoot of 1.68%, was very close to FPA, which had a response time of 0.644s and an overshoot of 0.81%. This comparison highlighted the advantages of the FPA algorithm, which is simple to use, requires fewer parameters to adjust, and takes less time than ACO. This study suggests the potential for implementing a hybrid FPA-ACO algorithm, leveraging the strengths of both algorithms.

Generation of multiwavelength cylindrical vector beams from a random fiber laser assisted with nonlinear amplifying loop mirror

In past decades, vector mode random fiber laser (RFL) has attracted much exploration and rapid development. In this work, we proposed and demonstrated a novel multiwavelength RFL that produces cylindrical vector beams (CVBs). The gain profile is manipulated by a homemade Sagnac loop filter assisted with the nonlinear amplifying loop mirror (NALM) mechanism to improve multi-wavelength oscillation capability. The CVBs are generated with the help of long-period fiber grating and the wavelength switchablity CVBs random fiber laser is obtained. The wideband spectrum multiwavelength CVBs with the maximum channel number of seventeen are realized with NALM. This currently holds the record for the highest number of wavelength channels of vector mode random lasers which holds great promise for free-space optical communication. Coherent-tunable low-coherence high-order modes and cylindrical vector mode random lasers utilizing wavelength tailoring have been realized with high mode purity. The proposed CVBs with modeless behavior have potential applications prospects in optical signal multiplexing, space optical communication, and speckle-free laser active imaging.

On the equivalence between steady-state Kalman filter and DPLL

Fundamental results in the literature showed that a class of Kalman filters (KF) converges to a digital phase lock loop (DPLL) structure. Results were proved for second- and third-order KFs. We extend these results to KFs of any order and derive in closed form the equivalent loop filter constants as a linear combination of the steady-state Kalman gains. We also give the inverse relation. Both closed-form relations involve Stirling numbers of the first or second kind. We implement both filters in a global navigation satellite system (GNSS) receiver and illustrate their equivalence with real-world data. These extended theoretical results provide a deeper understanding of the equivalence between KF and DPLL and may be of practical interest in highly dynamic scenarios to design and tune tracking filters.

Optimal loop filter design of a DC immunity single-phase PLL based single delay operator

Optimal loop filter design of a DC immunity single-phase PLL based single delay operator

A Review on Fundamentals of Noise-Shaping SAR ADCs and Design Considerations

A general overview of Noise-Shaping Successive Approximation Register (SAR) analog-to-digital converters is provided, encompassing the fundamentals, operational principles, and key architectures of Noise-Shaping SAR (NS SAR). Key challenges, including inherent errors in processing circuits, are examined, along with current advancements in architecture design. Various issues, such as loop filter optimization, implementation methods, and DAC network element mismatches, are explored, along with considerations for voltage converter performance. The design of dynamic comparators is examined, highlighting their critical role in the SAR ADC architecture. Various architectures of dynamic comparators are extensively explored, including optimization techniques, performance considerations, and emerging trends. Finally, emerging trends and future challenges in the field are discussed.

A Robust Vector-Tracking Loop Based on KF and RTS Smoothing for Shipborne Navigation

High-precision navigation systems are crucial for unmanned autonomous vessels. However, commonly used Global Navigation Satellite System (GNSS) signals are often severely affected by environmental obstruction, leading to reduced positioning accuracy or even the inability to locate. To address the issues caused by signal obstruction in high-precision navigation systems, the research presented in this paper proposes a vector-tracking loop (VTL) structure based on the forward Kalman Filter (KF) and the backward Rauch Tung Striebel (RTS) smoothing algorithm. The introduction of loop filters in the signal-tracking loop improves the tracking accuracy of the carrier and code, thereby enhancing the stability and robustness of the navigation system. The traditional scalar-tracking loop (STL), traditional VTL, and Kalman Filter (KF)-based VTL were compared through shipborne motion experiments, and the proposed method demonstrated superior signal-tracking capability and navigation accuracy. In the experiment, there were three blocking areas along the experimental path. The experimental results show that, when there are signal blockages of 12 s, 18 s, and 40 s, compared to the traditional VTL method, the proposed method can reduce the horizontal position error by 93.9%, 95.8%, and 94.5%, respectively, as well as the horizontal velocity error by 71.1%, 95.8%, and 97.6%, respectively.

Enhancing USVs navigation based on minimum error entropy of GPS vector tracking

In recent years, unmanned surface Vessels (USVs) have increasingly been used for river monitoring and hydrological surveys. USVs rely on global navigation satellite systems (GNSS) for navigation. However, signal blocking can cause the traditional GNSS vector tracking (VT) loop to increase the code phase and carrier frequency errors, leading to higher positioning errors that do not meet USVs’ requirements. To address this problem, we propose a VT method based on the minimum error entropy (MEE) in the signal tracking module. The MEE Kalman filter is adopted as the loop filter to mitigate code phase and carrier frequency errors, reduce non-Gaussian noise and random errors generated by signal blocking, and enhance the positioning accuracy and robustness of USV navigation. The measurement noise covariance of the loop filter was adjusted adaptively using the signal carrier-to-noise ratio. A field experiment was conducted using a commercial GNSS receiver as reference. The results demonstrate a 19.3% improvement in positioning accuracy compared with the traditional method in an open environment. Moreover, the proposed method maintains stable operation and achieves a 79.4% improvement in positioning accuracy during signal blocking. This novel algorithm offers a new concept for USV navigation systems to cope with signal blocking.

A Novel Approach for Realizing Loop-Filter in Low-Distortion Noise-Coupled ΣΔ Modulators

This paper presents an innovative general structure for a single-loop Sigma-Delta ([Formula: see text]) modulator that combines low-distortion and noise-coupled techniques to achieve high-resolution for low-power applications. The low-distortion technique adjusts the signal transfer function of the proposed structure to unity, while the noise-coupled technique enhances the order of quantization noise-shaping at the modulator output. These techniques were incorporated into the design to increase the modulator order without requiring additional operational amplifiers during its circuit implementation, resulting in a low-power modulator compared to similar structures. To reduce the number of required amplifiers, a second-order infinite impulse response (IIR) filter was used in the modulator loop filter, in place of two integrators. To assess the proposed structure’s performance, a third-order modulator sample was implemented and simulated for speech recognition applications, specifically, digital hearing aids, using 180[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The results indicate that for a third structure with a sampling rate of 64, an input sine signal of −6[Formula: see text]dBFS and a sampling frequency of 2.56[Formula: see text]MHz, the signal to noise plus distortion (SNDR) was 81.9[Formula: see text]dB, and the dynamic range (DR) was 88[Formula: see text]dB for a 20[Formula: see text]KHz bandwidth. The modulator’s power consumption was 126.9[Formula: see text][Formula: see text]W. Circuit and system-level simulations demonstrate the effectiveness of the proposed method.

Multi-wavelength Brillouin erbium-doped fiber laser with 40 GHz frequency shift interval assisted by Sagnac loop filter

Multi-wavelength Brillouin erbium-doped fiber laser with 40 GHz frequency shift interval assisted by Sagnac loop filter

A frequency meter based on Costas FLL for resonant accelerometers

The resonant accelerometer (RA) is an important part for high-performance inertial devices. And high accuracy frequency measurement is one of the key technology for RA. This paper developed a frequency meter based on Costas frequency lock loop (FLL). This structure is flexible as the analog input sinusodial voltage wave is converted into digital domain by an ADC and the frequency measurement function dealing with that voltage could be implemented only with digital circuits. The transfer function of the frequency meter is determined by the loop filter of the FLL and the closed system is always stable for PID controller. The noise in the loop is reshaped by a first order ∑-Δ modulator formed by the frequency meter loop, which relaxes the requirement for the accuracy of ADC. A test board for the frequency meter is implemented with a 24-bit ADC and FPGA, and achieves a noise of 1mHz/Hz at low frequency band, 7µHz/Hz around 50 Hz with a 40 kHz sinusodial input voltage.

A Highly Flexible Passive/Active Discrete-Time Delta-Sigma Receiver

This paper presents a fourth-order discrete-time direct RF-to-digital Delta-Sigma receiver architecture for flexible receivers with a wide frequency range. The use of a current-driven passive mixer with RF feedback enables high-Q bandpass filtering and relaxes the linearity requirement of the RF amplifier. In addition, the reconfigurable passive/active loop filter offers a good compromise between power consumption, linearity, and dynamic range. The other important feature of the proposed architecture is the use of a sampling frequency that is a divisor of the LO frequency. This solves several problems such as the upmixing of quantization noise, the need to reconfigure the Delta-Sigma loop when changing the LO frequency, and the use of two independent clocks for the LO and the sampling frequency. The circuit was implemented using 65 nm CMOS technology. The I/Q Direct Delta-Sigma receiver has an RF bandwidth of 20 MHz and a sampling frequency of 400 MHz. Measurement results show a very high dynamic range of up to 80 dB with a peak SNDR of 46 dB for a power consumption of 46 mW at 800 MHz.

Wavelength-tunable flat-top polarization-diversified fiber loop filter based on all-quarter-wave polarization transformation

Wavelength-tunable flat-top polarization-diversified fiber loop filter based on all-quarter-wave polarization transformation