A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD

Abstract

A dual-loop CDR (Clock and Data Recovery) is presented to recover digital data from 1 to 6.5 Gbps. The presented frequency acquisition technique is based on full rate clock architecture. By utilizing modified Digital Quadri-correlator Frequency Detector (DQFD) and Frequency Increment/Decrement Control circuit, the lock-in range is improved. Furthermore, the issue of state loss during wide frequency range detection is successfully mitigated. The inclusion of two control wires in the Coarse-fine Tuning VCO enables the utilization of separate loop filters in the dual loops, resulting in a more effective reduction of noise and jitter. Utilizing a 40-nm CMOS process, the presented CDR design has been implemented. The post-layout simulation results at 6.5 Gbps shows a P2P and root-mean-square jitter values are 17.1 ps and 5.79 ps, respectively, for the retimed data.