Loop Architecture Research Articles

Anti-disturbance Coordinated Path-following Control of Robotic Autonomous Surface Vehicles: Theory and Experiment

This paper presents a guidance and control law design method for coordinated path following of networked underactuated robotic autonomous surface vehicles (ASVs) under directed communication links. Each ASV is subject to model uncertainties and environment disturbances induced by wind, waves, and ocean currents. Antidisturbance coordinated path-following controllers are designed, featured with an inner-outer loop architecture. In the outer loop, a line-of-sight guidance scheme and graph theory are employed to design guidance laws for synchronized path following. In the inner loop, an extended state observer is developed to estimate the lumped disturbances, including the model uncertainties and environmental disturbances. Based on the estimated disturbances through the extended state observer, antidisturbance kinetic control laws are designed by resorting to a dynamic surface control method. The input-to-state stability of the closed-loop system is established by cascade theory and all error signals are uniformly ultimately bounded. Finally, the results of simulation and experiment are given to illustrate the effectiveness of the proposed antidisturbance coordinated path-following controllers for underactuated ASVs.

A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector

A high-order cascaded phase-locked loop (PLL) architecture using a sub-sampling delay-locked loop (DLL) is proposed to break the tradeoff between the loop bandwidth and the number of integrator in the feedback loop without significantly degrading the settling time or reference spur. A clock-skew-sampling phase detector is also proposed to extend the stable detection range of the sub-sampling phase detector. Implemented in a 65-nm CMOS process, a prototype of the proposed two-stage third-order cascaded PLL measures a 4.2- $\mu \text{s}$ settling time, 1.05-ps integrated jitter, and −113-dBc/Hz in-band phase noise at a 2.1-GHz output frequency while consuming 3.84 mW at 1.2-V supply voltage and occupying a core chip area of 0.043 mm2.

A learning system for adjustment processes based on human sensory perceptions

Creating, designing and adjusting products are essential decision processes underlying creative industries, such as painting, perfume, food and beverage industries. These processes require the participation and continuous supervision of professionals with highly-developed expert sensory abilities. Training of these experts is very complex due to the difficulty of transmitting intuitive knowledge obtained from perception. A new methodology for capturing this sensory expert knowledge that relies on a machine learning tool, previously trained with ‘state-action’ type patterns, jointly with an actions generator module, is proposed in this work. The method is based on a closed loop architecture together with the decomposition of complex sensory knowledge into basic elements capable of being handled by standard machine learning systems. A real case application to color-adjustment in the automotive paint manufacturing industry is presented showing the potential benefits of the method.

A Dual-Loop Synthesizer With Fast Frequency Modulation Ability for 77/79 GHz FMCW Automotive Radar Applications

The implementation of wideband mm-wave radars for automotive applications necessitates wideband, fast, and precise linear frequency modulation generation. In this paper, we propose to use dual-loop phase-locked loop (PLL) architecture for this task. The frequency modulation dynamics are analyzed for this architecture. The results are employed to implement a SiGe BiCMOS fully integrated 75–83 GHz frequency-modulated continuous-wave synthesizer. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism together with the dual-loop PLL architecture provides low loop bandwidth variation over the whole output frequency range, −97 dBc/Hz phase noise at 1-MHz offset, and maximal modulation rate of 100 GHz/ms.

Plug-and-Play Multicellular Circuits with Time-Dependent Dynamic Responses.

Synthetic biology studies aim to develop cellular devices for biomedical applications. These devices, based on living instead of electronic or electromechanic technology, might provide alternative treatments for a wide range of diseases. However, the feasibility of these devices depends, in many cases, on complex genetic circuits that must fulfill physiological requirements. In this work, we explored the potential of multicellular architectures to act as an alternative to complex circuits for implementation of new devices. As a proof of concept, we developed specific circuits for insulin or glucagon production in response to different glucose levels. Here, we show that fundamental features, such as circuit's affinity or sensitivity, are dependent on the specific configuration of the multicellular consortia, providing a method for tuning these properties without genetic engineering. As an example, we have designed and built circuits with an incoherent feed-forward loop architecture (FFL) that can be easily adjusted to generate single pulse responses. Our results might serve as a blueprint for future development of cellular devices for glycemia regulation in diabetic patients.

Comprehensible and dependable self-learning self-adaptive systems

Abstract Self-adaptivity enables flexible solutions in dynamically changing environments. However, due to the increasing complexity, uncertainty, and topology changes in cyber-physical systems (CPS), static adaptation mechanisms are insufficient as they do not always achieve appropriate effects. Furthermore, CPS are used in safety-critical domains, which requires them and their autonomous adaptations to be dependable. To overcome these problems, we extend the MAPE-K feedback loop architecture by imposing a structure and requirements on the knowledge base and by introducing a meta-adaptation layer. This enables us to continuously evaluate the accuracy of previous adaptations, learn new adaptation rules based on executable run-time models, and verify the correctness of the adaptation logic in the current system context. We demonstrate the effectiveness of our approach using a temperature control system. With our framework, we enable the design of comprehensible and dependable dynamically evolving adaptation logics.

A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master–Slave PLL Synthesis

This paper presents an ultralow power asynchronous logic transmitter operating at 1 Gpps that achieves pulse synthesis using a double phase-locked loop (PLL) architecture for applications exploiting large-scale neuronal interfacing with CMOS probes. The 4 GHz center frequency OOK transmitter synthesizes 500 ps duration pulses from a 31.25 MHz crystal oscillator using a cascade of a master and a slave PLL with the latter locked to the former. Both PLLs are implemented with CMOS digital cells and ring oscillator-based VCO. A prototype fabricated in a 130 nm RFCMOS process operates at a measured 5 pJ/pulse energy budget for an active area of 0.04 mm2. To generate timing references and packets for high data rate recording devices, the synthesizer core feeds also a logic interface operating at 250 MHz with four 1.2–3.3 V external parallel channels. From reset time, the master–slave PLL combination achieves locking in a measured time of 450 ns, settling is resolved in $\sim 4~\mu \text{s}$ , and the output pulses across the antenna load are generated with a 3.42 ps RMS jitter standard deviation. The obtained phase noise of a continuous OOK stream at 1 and 4 GHz, 1 MHz offset, is −103 and −93 dBc/Hz, respectively.

Design of Unambiguous Combined Tracking Loop for GNSS Complex Subcarrier Signal

Complex subcarrier modulation signal, is a kind of BOC signal which is used complex exponential function as subcarrier, has been widely applied in GNSS(Global Navigation satellite system). The existence of multiple correlation peaks of the autocorrelation function of the complex subcarrier signal, will cause the acquisition error and tracking to the side peak when the signal is synchronized. To solve this problem, an unambiguous combined tracking loop for complex subcarrier signals is proposed. In this loop architecture, the main loop completes the coarse synchronization with BPSK-like algorithm, and the assisted loop realizes the accurate tracking together main loop. In this paper, the dual estimate tracking algorithm and the side-peak cancellation scheme are employed respectively in the assisted loop. The performance of tracking accuracy and anti-multipath capability of the proposed architecture is analyzed, and the practicability is verified by using the actual collected data. Simulation and experimental results show that the tracking structure proposed in this paper is practical and has good performance of anti-noise and anti-multipath.

Comparision of new element designs for combined RF-Shim arrays at 7 T.

To identify novel concepts for RF-shim loop architectures suitable for 7T made of two concentric conducting loops fulfilling RF and DC functions, respectively, and to determine their relative SNR performance. The goal is to minimize interference between the two systems while making efficient use of the space closest to the body. We show by means of theoretical derivation of the frequency spectrum that the proposed two-loop structure exhibits an anti-resonant null and a resonant peak in the frequency domain. The proposed structure is comprised of two concentric wire loops either arranged as nested loops or in the form of a coaxial cable, in which the two conductors carry the RF and shim signals, respectively. We use theory, simulation, and phantom measurements to obtain frequency spectra and SNR maps for the proposed structures. Retained SNR is found to be 75% in the coaxial loop and ranges from 57% to 67% in three different coaxial configurations. We have found both implementations to be a viable concept for the use in RF-shim devices if remaining SNR limitations can be overcome. We have investigated two new design modalities in 7T RF-shim coil design that separate the RF and shim conductors such that the previously proposed toroidal chokes are eliminated - thereby removing undesired additional loss, bulk, and design complexity.

PLL architecture with a composite PFD and variable loop filter

A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when Δφ > π and provides a lower-gain and loop BW during tracking when Δφ <; π as well as after lock-in. The PLL system is designed to ensure stability by maximising and equalising phase margin in both the linear as well as non-linear operations. The transfer characteristics of composite PFD are free from the blind zone and also found possible to eliminate glitches from the output. A prototype of PLL operating at 2.56 GHz developed on 180 nm complementary metal-oxide-semiconductor process is found to achieve reference spur of -71.4 dBc, lock time of 2.05 μs, peak-to-peak jitter of 3.412 ps, phase noise of -110 dBc/Hz at 100 kHz and final placement area of 0.244 mm 2 .

Lightweight S-Box Architecture for Secure Internet of Things

Lightweight cryptographic solutions are required to guarantee the security of Internet of Things (IoT) pervasiveness. Cryptographic primitives mandate a non-linear operation. The design of a lightweight, secure, non-linear 4 × 4 substitution box (S-box) suited to Internet of Things (IoT) applications is proposed in this work. The structure of the 4 × 4 S-box is devised in the finite fields GF (24) and GF ((22)2). The finite field S-box is realized by multiplicative inversion followed by an affine transformation. The multiplicative inverse architecture employs Euclidean algorithm for inversion in the composite field GF ((22)2). The affine transformation is carried out in the field GF (24). The isomorphic mapping between the fields GF (24) and GF ((22)2) is based on the primitive element in the higher order field GF (24). The recommended finite field S-box architecture is combinational and enables sub-pipelining. The linear and differential cryptanalysis validates that the proposed S-box is within the maximal security bound. It is observed that there is 86.5% lesser gate count for the realization of sub field operations in the composite field GF ((22)2) compared to the GF (24) field. In the PRESENT lightweight cipher structure with the basic loop architecture, the proposed S-box demonstrates 5% reduction in the gate equivalent area over the look-up-table-based S-box with TSMC 180 nm technology.

Theoretical analysis of unambiguous 2-D tracking loop performance for band-limited BOC signals

Code-tracking accuracy, an important attribute of receiver performance assessment, depends both on characteristics of the ranging signal being tracked and on the structure of the tracking channel. The implementation of binary offset carrier (BOC) modulated signals and the development of new tracking channel structures with a two-dimensional (2-D) loop architecture, in which both the code and subcarrier delays are estimated independently by two separate tracking loops, have resulted in the theories of 2-D loop tracking performance being of increased interest. However, the theories of tracking performance in white noise for band-limited BOC signals using the most representative and most mature 2-D tracking method are still not mature. Therefore, we present the exact expression for tracking performance prediction for limited front-end bandwidths to show how well double estimator technique (DET) could perform for given conditions. While evaluation of the exact expression requires numerical integration, a simple yet accurate closed-form analytical approximation is also provided for a more intuitive description of tracking performance. Moreover, we present a bandwidth-dependent, quasi-optimal, discriminator parameter selection rule to simplify the work of receiver designers while improving tracking performance. These results can provide further guidance for the design, parameters selection, and optimization of the receiver.

Design of an ultra-low power, low complexity and Low Jitter PLL with digitally controlled oscillator

This paper proposes a new area-efficient, low-power and low-jitter phased-locked loop (PLL) architecture working off a low frequency reference. In this paper, new PLL is proposed with a new locking procedure with low complexity which results in ultra low power design. The main challenge to design the proposed PLL is to keep the area small while meeting the required low jitter. The proposed method was designed using only two up-down counters for finding the reference frequency. An efficient glitch removal filter and new low power DCO also introduced in this paper. The proposed DCO achieves a reasonably high resolution of 1ps. The PLL architecture was demonstrated for different frequency ranges from 100-400 MHz. The power consumption of proposed PLL at 500 MHz frequency is 820 μW. The proposed PLL is simulated in 180 nm with Tanner EDA and verified.

An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications

In a system on a chip (SoC), there are several long global wires that typically limit the maximum SoC clock speed. Therefore, through-silicon via (TSV) technology has been proposed to shorten the length of the global wires. However, the TSV delay variation phenomenon created during the manufacturing process may prevent SoC systems from working properly. This TSV delay variation problem affects data transmission between dies. In this paper, we present an all-digital delay-locked loop (ADDLL) architecture to synchronize clock signals between two dies. We implement the proposed ADDLL in TSMC 90-nm CMOS process with standard cells, which can tolerate process, voltage, and temperature (PVT) variations. In addition, the ADDLL architecture can overcome the TSV delay variation problem using only a single TSV channel. The proposed ADDLL can operate in an input frequency range of 195–960 MHz with a maximum phase error of less than 40.6 ps.

Diffloop: a computational framework for identifying and analyzing differential DNA loops from sequencing data.

SummaryThe 3D architecture of DNA within the nucleus is a key determinant of interactions between genes, regulatory elements, and transcriptional machinery. As a result, differences in DNA looping structure are associated with variation in gene expression and cell state. To systematically assess changes in DNA looping architecture between samples, we introduce diffloop, an R/Bioconductor package that provides a suite of functions for the quality control, statistical testing, annotation, and visualization of DNA loops. We demonstrate this functionality by detecting differences between ENCODE ChIA-PET samples and relate looping to variability in epigenetic state.Availability and implementationDiffloop is implemented as an R/Bioconductor package available at https://bioconductor.org/packages/release/bioc/html/diffloop.htmlSupplementary information Supplementary data are available at Bioinformatics online.

Editor’s Note

The year of 2017 starts with good news to JIS. It was classified as B3 in the Qualis index for the Computer Science area. Qualis is the journal classification index of CAPES (Brazilian governmental agency for improvement of higher education personnel), and the classification refers to the period of 2013-2016. In the previous period, JIS was classified as B4. This indicates that JIS is being increasingly recognized as an interesting publication vehicle. JIS is also included in Qualis for other areas, such as Engineering, Mathematics/Statistics, Biotechnology, Communication &amp; Information, and Interdisciplinary area. This is an important achievement for us, and certainly motivates us to keep working hard to attract good quality papers and authors.Another important news in 2017 is the participation of Dr. Cléber Gimenez Corrêa, from University of São Paulo, who joint us as JIS Assistant Editor. His work has been fundamental to prepare this one and the following issues. I would like to warmly welcome him!This first issue of JIS in 2017 contains extended versions of five papers selected among the best full papers of SBGames 2014 --- XIII Brazilian Symposium on Games and Digital Entertainment. I would like to thank the authors and Esteban Clua, for acting as guest editor for this special issue, and invite you to read his editorial in the following.In line with the theme of the special issue, we also have in this issue an original paper by Marcelo Zamith, Luis Valente, Bruno Feijó, Mark Joselli, and Esteban Clua, entitled "Parallel game architectures with tardiness policy and workload balance". The authors developed an adaptive game loop architecture based on tardiness control to adapt task operation according to the current hardware load conditions at a given moment. Their adaptive game loop is able to create game task list scheduling, considering multi-core processors.I would like to thank the authors and reviewers that contributed to this issue of JIS, and I hope it fulfills your expectations. JIS Editorial Board is looking forward to receiving your contributions.

A 5GHz Digital Fractional- $N$ PLL Using a 1-bit Delta–Sigma Frequency-to-Digital Converter in 65 nm CMOS

A highly digital two-stage fractional- $N$ phase-locked loop (PLL) architecture utilizing a first-order 1-bit $ \Delta \!\Sigma $ frequency-to-digital converter (FDC) is proposed and implemented in a 65nm CMOS process. Performance of the first-order 1-bit $ \Delta \!\Sigma $ FDC is improved by using a phase interpolator-based fractional divider that reduces phase quantizer input span and by using a multiplying delay-locked loop that increases its oversampling ratio. We also describe an analogy between a time-to-digital converter (TDC) and a $ \Delta \!\Sigma $ FDC followed by an accumulator that allows us to leverage the TDC-based PLL analysis techniques to study the impact of $ \Delta \!\Sigma $ FDC characteristics on $ \Delta \!\Sigma $ FDC-based fractional- $N$ PLL (FDCPLL) performance. Utilizing proposed techniques, a prototype PLL achieves 1 MHz bandwidth, −101.6 dBc/Hz in-band phase noise, and $ {\textrm {1.22 ps}_{\textrm {rms}}}$ (1 kHz–40 MHz) jitter while generating 5.031GHz output from 31.25MHz reference clock input. For the same output frequency, the stand-alone second-stage fractional- $N$ FDCPLL achieves 1MHz bandwidth, −106.1dBc/Hz in-band phase noise, and $ {\textrm {403 fs}_{\textrm {rms}}}$ jitter with a 500MHz reference clock input. The two-stage PLL consumes 10.1mW power from a 1V supply, out of which 7.1 mW is consumed by the second-stage FDCPLL.

Hybrid Structure Multichannel All-Fiber Current Sensor.

We have experimentally developed a hybrid-structure multi-channel all-fiber current sensor with ordinary silica fiber using fiber loop architecture. According to the rationale of time division multiplexing, the sensor combines parallel and serial structures. The purpose of the hybrid-structure multi-channel all-fiber current sensor is to get more information from the different measured points simultaneously. In addition, the hybrid-structure fiber current sensor exhibited a good linear response for each channel. A three-channel experiment was performed in the study and showed that the system could detect different current positions. Each channel could individually detect the current and needed a separate calibration system. Furthermore, the three channels will not affect each other.

A transcription network of interlocking positive feedback loops maintains intracellular iron balance in archaea.

Iron is required for key metabolic processes but is toxic in excess. This circumstance forces organisms across the tree of life to tightly regulate iron homeostasis. In hypersaline lakes dominated by archaeal species, iron levels are extremely low and subject to environmental change; however, mechanisms regulating iron homeostasis in archaea remain unclear. In previous work, we demonstrated that two transcription factors (TFs), Idr1 and Idr2, collaboratively regulate aspects of iron homeostasis in the model species Halobacterium salinarum. Here we show that Idr1 and Idr2 are part of an extended regulatory network of four TFs of the bacterial DtxR family that maintains intracellular iron balance. We demonstrate that each TF directly regulates at least one of the other DtxR TFs at the level of transcription. Dynamical modeling revealed interlocking positive feedback loop architecture, which exhibits bistable or oscillatory network dynamics depending on iron availability. TF knockout mutant phenotypes are consistent with model predictions. Together, our results support that this network regulates iron homeostasis despite variation in extracellular iron levels, consistent with dynamical properties of interlocking feedback architecture in eukaryotes. These results suggest that archaea use bacterial-type TFs in a eukaryotic regulatory network topology to adapt to harsh environments.

Matrix phase detector for high bandwidth and low jitter frequency synthesis

A phase-locked loop (PLL) architecture based on a 2D phase comparator matrix is introduced. In its general form, multiple phases of the input reference clock are compared with multiple phases of the feedback clock, allowing for wider bandwidth (BW) and lower phase noise generation of the PLL. Based on matrix phase detector architecture, a 6.25 GHz PLL achieving 5 GHz BW and exhibiting 55 fs-rms jitter is designed in 28 nm CMOS bulk technology.