Look-ahead Computation Research Articles

A low-latency real-time PAM-4 receiver enabled by deep-parallel technique

High-speed photonic networks using digital signal processing (DSP) techniques are flourishing nowadays to meet the high-bandwidth requirements of modern bandwidth-thirsty applications in a cost-effective manner. However, the additional latency introduced by DSP is hindering the latency-critical applications. In this paper, a FPGA-based real-time low-latency four-level pulse amplitude modulation (PAM-4) receiver including digital adaptive equalization (DAE) is designed and implemented by using a latency-reducing parallel architecture. The DSP-introduced latency in the receiver end is analyzed in detail. As for DAE parallel implementation, a novel re-allocation scheme is proposed to cope with the issue of the dependency of the output on the successive input samples, and a look-ahead computation technique is introduced to improve the adaptive update efficiency. A real-time PAM-4 receiver is demonstrated in an experimental fiber link with 2.5 Gbit/s data rate for the performance evaluation. Compared with offline processing with MATLAB, the BER performance has little deterioration at 7% FEC limit of 1 × 10−3. With the help of the proposed deep-parallel technique, the DSP-introduced latency is reduced to 0.4μs on average, which better meets the requirements of latency-sensitive user cases in 5G networks. Furthermore, the real-time PAM-4 receiver could be flexibly reconfigured for various scenarios with low-latency requirements, and the latency-efficient parallel technique as well as the latency analysis method can also be extended to high-speed hardware implementation for data rates up to 100 Gbit/s or more.

Look-Ahead with Mini-Bucket Heuristics for MPE

The paper investigates the potential of look-ahead in the con-text of AND/OR search in graphical models using the Mini-Bucket heuristic for combinatorial optimization tasks (e.g., MAP/MPE or weighted CSPs). We present and analyze the complexity of computing the residual (a.k.a Bellman update) of the Mini-Bucket heuristic and show how this can be used to identify which parts of the search space are more likely to benefit from look-ahead and how to bound its overhead. We also rephrase the look-ahead computation as a graphical model, to facilitate structure exploiting inference schemes. We demonstrate empirically that augmenting Mini-Bucket heuristics by look-ahead is a cost-effective way of increasing the power of Branch-And-Bound search.

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Phase Estimation Methods for Optical Coherent Detection Using Digital Signal Processing

The advent of digital signal processing (DSP) to optical coherent detection means that more phase estimation options are available, compared to the earlier generation where phase-locked loops (PLLs) were invariably deployed in synchronous coherent receivers. Several phase estimation methods are numerically modeled: the maximum a posteriori (MAP) phase estimate, decision directed estimate, power law-Wiener filter estimate and power law-PLL estimate. An asynchronous coherent detection case is also modeled. The phase estimates are evaluated with respect to their tolerance of finite laser linewidth and their suitability for implementation in a parallel digital processor. Laser phase noise causes transmission system performance to be degraded by excess bit errors and cycle slips. The optimal phase estimate is the MAP estimate, and it is also included as a baseline. The power law-Wiener filter phase estimate is found to perform only marginally worse than the MAP estimate. It must be recast using a look-ahead computation to be implemented in a parallel digital processor, and the impact is investigated of the increase in the number of computations required. Differential logical detection is often used to reduce the impact of cycle slip events, and the implications of this operation on the bit error rate are studied. It is found that by choosing the correct FEC scheme differential logical detection does not increase the Q-factor penalty.

Area-efficient high-throughput MAP decoder architectures

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In this paper, we present block-interleaved pipelining (BIP) as a new high-throughput technique for MAP decoders. An area-efficient symbol-based BIP MAP decoder architecture is proposed by combining BIP with the well-known look-ahead computation. These architectures are compared with conventional parallel architectures in terms of speed-up, memory and logic complexity, and area. Compared to the parallel architecture, the BIP architecture provides the same speed-up with a reduction in logic complexity by a factor of M, where M is the level of parallelism. The symbol-based architecture provides a speed-up in the range from 1 to 2 with a logic complexity that grows exponentially with M and a state metric storage requirement that is reduced by a factor of M as compared to a parallel architecture. The symbol-based BIP architecture provides speed-up in the range M to 2M with an exponentially higher logic complexity and a reduced memory complexity compared to a parallel architecture. These high-throughput architectures are synthesized in a 2.5-V 0.25-/spl mu/m CMOS standard cell library and post-layout simulations are conducted. For turbo decoder applications, we find that the BIP architecture provides a throughput gain of 1.96 at the cost of 63% area overhead. For turbo equalizer applications, the symbol-based BIP architecture enables us to achieve a throughput gain of 1.79 with an area savings of 25%.

Eliminating the Fanout Bottleneck in Parallel Long BCH Encoders

Long BCH codes can achieve about 0.6-dB additional coding gain over Reed-Solomon codes with similar code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fanout, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. In this paper, a novel scheme based on look-ahead computation and retiming is proposed to eliminate the effect of large fanout in parallel long BCH encoders. For a (2047, 1926) code, compared to the original parallel BCH encoder architecture, the modified architecture can achieve a speedup of 132%.

Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN

We present low-power and high-speed algorithms and architectures for complex adaptive filters. These architectures have been derived via the application of algebraic and algorithm transformations. The strength reduction transformation is applied at the algorithmic level as opposed to the traditional application at the architectural level. This results in a power reduction by 21% as compared with the traditional cross-coupled structure. A fine-grained pipelined architecture for the strength-reduced algorithm is then developed via the relaxed lookahead transformation. This technique, which is an approximation of the conventional lookahead computation, maintains the functionality of the algorithm rather than the input-output behavior. Convergence analysis of the proposed architecture is presented and supported via simulation results. The pipelined architecture allows high-speed operation with negligible hardware overhead. It also enables an additional power savings of 39 to 69% when combined with power-supply reduction. Thus, an overall power reduction ranging from 60-90% over the traditional cross-coupled architecture is achieved. The proposed architecture is then employed as a receive equalizer in a communication system for a data rate of 51.84 Mb/s over 100 m of UTP-3 wiring in an ATM-LAN environment. Simulation results indicate that speedups of up to 156 can be achieved with about a 0.8-dB loss in performance.

A parsing method for context-free languages using bottom-up lookahead computation

A new parsing algorithm of context-free languages using bottom-up computation of lookahead information is presented. Earley's algorithm uses a great number of items during enumeration to recognize a context-free language. If items with lookahead fields are used, the number of items can be reduced, but item spacing is considerably increased. The method presented here may reduce the number of items during enumeration without using lookahead fields of items. The computation of lookahead information takes place in a bottom-up manner. It is not necessary to compute lookahead information until it is required during enumeration.

Pipelined adaptive DFE architectures using relaxed look-ahead

Fine-grain pipelined adaptive decision-feedback equalizer (ADFE) architectures are developed using the relaxed look-ahead technique. This technique, which is an approximation to the conventional look-ahead computation, maintains functionality of the algorithm rather than the input-output behavior. Thus, it results in substantial hardware savings as compared to either parallel processing or look-ahead techniques. Pipelining of the decision feedback loop and the adaptation loop is achieved by the use of delay relaxation and sum relaxation. Both the conventional and the predictor form of ADFE have been pipelined. Results of the convergence analysis of the proposed algorithms are also provided. The performance of the pipelined algorithms for the equalization of a magnetic recording channel is studied. It is shown that the conventional ADFE results in an SNR loss of about 0.6 dB per unit increase in the speed-up factor. The predictor form of ADFE is much more robust and results in less than 0.1 dB SNR loss per unit increase in the speed-up factor. Speed-ups of up to 8 and 45 have been demonstrated for the conventional and predictor forms of ADFE.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design, performance, and extensions of the RAM-DFE architecture

The design and performance of an adaptive RAM-Decision feedback equalizer integrated circuit (RAM-DFE IC) for magnetic recording channels is presented. The 0.8 /spl mu/m BICMOS digital chip has been integrated with discrete analog components in a 54 Mbps read channel. Description of the IC implementation details techniques to reduce latency and outlines tradeoffs between performance and complexity. In an effort to achieve higher throughput, alternative decision feedback loop architectures based on look-ahead computation are evaluated. A hybrid RAM/linear architecture is found to approach 150 Mbps throughput with implementational advantages over both RAM and linear feedback filters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Vectorization of the DLMS transversal adaptive filter

The subject of high sampling rate realizations for transversal adaptive filters is addressed. In particular, a vectorized version of the delayed least mean squares (DLMS) algorithm is derived using look-ahead computation techniques. The resulting parallel algorithm is then mapped onto a linear array of highly pipelined processing modules, which can accept an input vector of arbitrary length, and compute the corresponding output vector in a single clock cycle. The proposed system is shown to be capable of implementing transversal adaptive filters at sampling rates which are theoretically without bound. The performance of the proposed system is analyzed and simulation results are presented to verify the convergence properties of the algorithm under varying degrees of vectorization.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Algebraic recurrence transformations for massive parallelism

Recursions generally present a bottleneck for the mapping of algorithms onto massively parallel architectures. A great deal of work has been done showing how to break this bottleneck using look-ahead computation. By applying results of P. Kogge and H. Stone (IEEE Trans. Comput., vol. C-22, pp. 786-793, 1973) it was shown that few basic algebraic axioms are sufficient for speeding up recursions by look-ahead techniques. This allows one to generalize architectures derived for special cases. Furthermore, it was shown that the look-ahead computation technique, known to date only for recursions with up to two operations, can be generalized to recursions with n operations. This allows the design of massively parallel architectures for more complex recursions. General algebraic examinations of expressions as described here can be applied to feedforward expressions, as well.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed VLSI architectures for Huffman and Viterbi decoders

Pipelined and parallel architectures for high-speed implementation of Huffman and Viterbi decoders (both of which belong to the class of tree-based decoders) are presented. Huffman decoders are used for lossless compression. The Viterbi decoder is commonly used in communications systems. The achievable speed in these decoders is inherently limited due to the sequential nature of their computation. This speed limitation is overcome using a previously proposed technique of look-ahead computation. The incremental computation technique is used to obtain efficient parallel (or block) implementations. The decomposition technique is exploited to reduce the hardware complexity in pipelined Viterbi decoders, but not in Huffman decoders. Logic minimization is used to reduce the hardware overhead complexity in pipelined Huffman decoders.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Pipelining in algorithms with quantizer loops

High-speed implementation of signal processing algorithms for digital transmission is addressed. The internal feedback or recursion in these algorithms makes it difficult to implement recursive systems concurrently using either pipelining or parallelism. In the past, look-ahead computation techniques were successfully applied to create necessary concurrency in linear recursive and some nonlinear recursive operations (such as the add-compare-select operation). Novel computation approaches are proposed, and the look-ahead technique is extended to pipeline the feedback loops containing finite-level quantizers. Approaches to pipeline piecewise-linear recursive systems are presented. The proposed architectures are suitable for real-time high-speed implementation of quantizer loop operations where the levels of quantizer and the order of the loops are small. >

Pipelining in dynamic programming architectures

Novel computation techniques to achieve fine-grain pipelining in forward dynamic programming (DP) architectures are proposed. The sequential DP algorithm is proposed using fewer finer grain pipelined processors, and increased hardware efficiency is achieved by using a novel computation sequence. Look-ahead computation is used to obtain a concurrent DP algorithm, and it is used in combination with an appropriate computation sequence to achieve further pipelining in DP architectures. The finer grain pipelined architectures are mapped to ring and mesh processor arrays, and approximately the same iteration rate is achieved as the coarse-grain pipelined architectures, but with use of much less hardware. The design of interleaved architectures using multiple clocks is also outlined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Techniques for high-speed implementation of nonlinear cancellation

The authors present techniques for breaking the bottleneck caused by delays in the feedback loop, which can severely limit the maximum data rate of a detector, operating with nonlinear cancellation (NLC). The authors first show how to simplify the loop to avoid high-speed switching of analog signals by using multiple decision elements, each with a different threshold level. The authors then show how to use lookahead computation to increase the delay permissible in the feedback loop. The authors describe nonlinear cancellation, and outline some of the problems of implementing NLC at high data rates. Techniques for overcoming these problems are developed and are illustrated with the example of a simple one-tap NLC. The authors describe how to generalize the techniques to more complex NLCs and present some more examples.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Finite word effects in pipelined recursive filters

High sample rate recursive filtering can be achieved by transforming the original filters to higher-order filters using the scattered look-ahead computation technique (which relies upon pole-zero cancellation). Finite word-length implementation of these filters leads to inexact pole-zero cancellation. This necessitates a thorough study of finite word effects in these filters. Theoretical results on roundoff and coefficient quantization errors in these filters are presented. It is shown that to maintain the same error at the filter output, the word length needs to be at most increased by log/sub 2/ log/sub 2/ 2M bit for a scattered look-ahead decomposed filter (where as M is the level of loop pipelining). This worst case corresponds to the case when all poles are close to zero. For M between two and eight, the word length needs to be increased only by 1 or 2 bit. Contrary to common beliefs, it is concluded that pole-zero canceling scattered look-ahead pipelined recursive filters have good finite word error properties.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parallel construction of SLR (1) and LALR (1) parsers

The generation of an LR parser consists of constructing a parse table, with one row per state (in a push-down automaton), and one column per terminal symbol. Traditionally, this is carried out row by row, with the computation of one row depending (potentially) on all the others. We present a technique for carrying out the lookahead computation of SLR (1) and LALR (1) parsers in a completely parallel fashion. Our technique performs the computation by column, rather than by row. We show that the computation is totally independent for each column, making it ideal for parallelization. The speedup factor of the technique is min (N, T), whereN is the number of processors andT is the number of terminal symbols in the user's grammar.

Concurrent architectures for two-dimensional recursive digital filtering

Efficient architectures are presented for high-speed implementation of two-dimensional recursive digital filters of direct form and local state-space form. Unlike one-dimensional recursive systems, two-dimensional recursive digital filter algorithms have a large amount of inherent concurrency. The authors exploit this concurrency to derive fine-grain pipelined and one-dimensional block architectures for implementation of two-dimensional recursive digital filters by appropriate interleaving (or indexing) of the input samples, without requiring any algorithm transformation and without any hardware overhead. They then extend the look-ahead computation and incremental computation techniques to to dimensions and use them to derive two-dimensional incremental block filter architectures. The multiplication complexity of the two-dimensional incremental block filter is determined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Concurrent cellular VLSI adaptive filter architectures

Previous approaches to high-sampling-rate adaptive filter implementations have been based on word-level pipelined word-parallel (or block) realizations. In this paper, we show that adaptive filters can be implemented in an area-efficient manner by first using pipelining to the maximum possible extent, and then using block processing in combination with pipelining if further increase in sampling rate is needed. We show that, with the use of a decomposition technique, high-speed realizations can be achieved using pipelining with a logarithmic increase in hardware (the block realizations require a linear increase in hardware). We derive pipelined word-parallel realizations of high-sampling-rate adaptive lattice filters using the techniques of look-ahead computation decomposed state update implementation, and incremental output computation. These three techniques combined make it possible to achieve asymptotically optimal complexity realizations (i.e., the same complexity asymptotically as nonrecursive systems) of high-speed adaptive lattice filters (in both bit-serial and bit-parallel methodologies) and provide a system solution to high-speed adaptive filtering. The adaptive lattice filter structures are ideal for high-sampling-rate implementations, since the error residuals of a particular stage are adapted order-recursively based on those of the previous stage, and the coefficient update recursion inside each stage is linear in nature. An example of a normalized stochastic gradient adaptive lattice filter is presented, and its complexity, latency, and implementation methodology tradeoffs are studied.