Long-term Data Retention Research Articles

Demonstration of scaling and monolithic stacking for higher integration of integrated circuit using c-axis aligned crystalline oxide semiconductor FET

C-axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs exhibit extremely low off-state leakage current and thus are suitable for low-power devices. Furthermore, CAAC-OS FETs can be integrated in the back end of line process and are promising as memory devices. For higher integration using the CAAC-OS FETs, we examined scaling and monolithic stacking. In addition, we present a 3D dynamic random access memory prototype, which is formed using three-layer monolithically stacked CAAC-OS FETs on a Si-CMOS and exhibits long-term data retention owing to the ultralow off-leakage current. These techniques will contribute to higher speed and integration of memory devices.

Ultrafast Non-Volatile Floating-Gate Memory Based on All-2D Materials.

The explosive growth of massive-data storage and the demand for ultrafast data processing require innovative memory devices with exceptional performance. 2D materials and their van der Waal heterostructures with atomically sharp interfaces hold great promise for innovations in memory devices. Here, this work presents non-volatile, floating-gate memory devices with all functional layers made of 2D materials, achieving ultrafast programming/erasing speeds (20ns), high extinction ratios (up to 108), and multi-bit storage capability. These devices also exhibit long-term data retention exceeding 10 years, facilitated by a high gate-coupling ratio (GCR) and atomically sharp interfaces between functional layers. Additionally, this work demonstrates the realization of an "OR" logic gate on a single-device unit by synergistic electrical and optical operations. The present results provide a solid foundation for next-generation ultrahigh-speed, ultralong lifespan, non-volatile memory devices, with a potential for scale-up manufacturing and flexible electronics applications.

A floating-gate field-effect transistor memory device based on organic crystals with a built-in tunneling dielectric by a one-step growth strategy.

A floating-gate organic field-effect transistor (FG-OFET) memory device is becoming a promising candidate for emerging non-volatile memory applications due to the advantages of its sophisticated data-storage mechanism and reliable long-term data retention capacity. However, a conventional FG-OFET memory device suffers from complex fabrication technologies and poor mechanical flexibility, which limits its practical applications. Here, we propose a facile one-step liquid-surface drag coating strategy to fabricate a layered stack of 2,8-difluoro-5,11-bis(triethylsilylethynyl) anthradithiophene (Dif-TES-ADT) crystals and high-quality insulating polymer polystyrene (PS). The liquid surface enhances the spreading area of an organic solution and facilitates the unidirectional growth of organic crystals. In the bilayer-structured blend, the bottom PS polymer and the top Dif-TES-ADT semiconductor serve as a tunneling dielectric and an active memory layer of an FG-OFET memory device, respectively. Consequently, a flexible FG-OFET memory device with a large memory window of 41.4 V, a long retention time of 5000 s, and a high current ON/OFF ratio of 105 could be achieved, showing the best performance ever reported for organic thin film-based FG-OFET memory devices. In addition, multi-level data storage (3 bits per cell) can be achieved by tuning the gate voltage magnitude. Our work not only provides a general strategy for the growth of high-quality organic crystals, but also paves the way towards high-performance flexible memory devices.

Optimal Data Decoding Strategies for Product-Coded Sequential Media Recording Via Latin Squares

In sequential media recording, such as found in tape data storage, data are typically accessed by reading signals from the beginning to the end of the recording medium in a streaming mode, which makes it unsuitable for random write accesses. However, sequential media is usually the preferred method for cold data storage in long-term data retention scenarios. In this study, we propose to increase the durability of sequential media by encoding data with locally recoverable codes (LRCs) both within and across different storage units creating a multidimensional product code external to the product code already implemented in the hardware. This way, local LRCs provide protection across the medium, whereas the LRCs spanning across different cartridges will provide global protection, which requires multiple drives and cartridges to help with the local decoding. Since global decoding is extremely costly, we require data allocation strategies that would use library resources efficiently. More specifically, we propose optimal data decoding and allocation strategies that would ensure minimum repair latency/communication cost in a global decoding setting for a given data request when local data reconstruction is not an option. We furthermore conduct analysis to find closed-form expressions and/or bounds on the overall latency/communication cost for product-coded systems under maintenance.

About Some Features of the Existence of the Humanities in the Digital Age

In the digital age, the humanities have undergone changes as new technologies have opened up new opportunities for research and interaction. Scientists now have access to huge amounts of data and can use computational methods for analysis, leading to new discoveries. However, the digital age also poses challenges, such as the need for long-term data retention. As the field of humanities continues to evolve, scientists must cope with these challenges and use the opportunities provided by the digital age to advance their research and interact with society in new and innovative ways.

A physical model for long term data retention characteristics in 3D NAND flash memory

An Activated Barrier Double Well Thermionic Emission (ABDWT) model is used to simulate long-term Data Retention (DR) in 3D NAND Flash memory cells. The contribution due to only charge De-Trapping (DT) when adjacent cells are at the same charged state and additional contribution due to charge Lateral Migration (LM) when adjacent cells are at different charged states are modeled. The Temperature (T), Program Level (PL), and Erase-Program Cycle (EPC) impacts are studied. The model simulations are verified against the experimental data from various published reports with consistent model parameters. It is shown that at higher temperatures and programming levels, the data retention increases for DT component, whereas LM component increases with the temperature and the lateral electric field.

A Low Power‐consumption and Transient Nonvolatile Memory Based on Highly Dense All‐Inorganic Perovskite Films (Adv. Electron. Mater. 9/2022)

Intelligent Electronics Highly crystalline CsPbBr3 films with dense and well-connected grains, as well as uniform thickness, are fabricated by a solution-processable two-step spin-coating method. Memory devices based on such films exhibit low power consumption, long-term data retention and transient behavior, which are desirable for next generation data storage devices and neuromorphic computing. More details can be found in article number 2101412 by Xiuru Xu, Zhengchun Peng, and co-workers.

THE ENHANCEMENTS IN STORAGE CAPACITY AND LONG-TERM DATA RETENTION OF MULTIDIMENSIONAL FLASH MEMORY IN MODERN MICROCIRCUIT APPLICATIONS

Generally, flash memory is a type of permanent memory for computers in which the contents can be reprocessed or erased electronically. Compared to programmable read-only memory that can erase electricity, operations on it can be performed on modules located in different locations. Flash memory is much less expensive than EEPROM, which is why it has become a dominant technology. Especially, in situations, this stable and long-term data retention is required. Its use is allowed in various cases like digital audio players, photo and video cameras, mobile phones and smartphones, and specialized Android applications on the memory card. Additionally, it is also used on USB flash drives, traditionally used to store and transfer information between computers. The proposed model provides enhancements to the storage capacity of various flash memory modules. In a saturation point, the proposed model achieved 93.03% of NOR Memory management, 89.31% of NAND Memory management, 94.25% of Ferroelectric RAM Memory management, and 94.53% of Magnetic RAM Memory management, 96.05% of Ovonic Unified Memory management and 96.16% of Salcogenide RAM Memory management.

Total Ionizing Dose Effects on Long-Term Data Retention Characteristics of Commercial 3-D NAND Memories

This article evaluates the data retention characteristics of irradiated multilevel-cell (MLC) 3-D NAND flash memories. We irradiated the memory chips by a Co-60 gamma-ray source for up to 50 krad(Si) and then wrote a random data pattern on the irradiated chips to find their retention characteristics. The experimental results show that the data retention property of the irradiated chips is significantly degraded when compared to the un-irradiated ones. We evaluated two independent strategies to improve the data retention characteristics of the irradiated chips. The first method involves high-temperature annealing of the irradiated chips, while the second method suggests preprogramming the memory modules before deploying them into radiation-prone environments.

Controllable resistive switching of STO:Ag/SiO2-based memristor synapse for neuromorphic computing

• STO:Ag/SiO 2 -based bilayer memristor has been fabricated for both digital and analog resistive switching. • A stable analog switching performance has been achieved in STO:Ag/SiO 2 bilayer based memristors. • Several essential synaptic functions as LTP, LTD, SRDP, PPF, and PTP have been successfully emulated. • The learning feature as spike-time dependent plasticity (STDP) has been mimicked, demonstrating the feasibility of STO:Ag/SiO 2 -based device for neuromorphic applications. Resistive random-access memory (RRAM) is a promising technology to develop nonvolatile memory and artificial synaptic devices for brain-inspired neuromorphic computing. Here, we have developed a STO:Ag/SiO 2 bilayer based memristor that has exhibited a filamentary resistive switching with stable endurance and long-term data retention ability. The memristor also exhibits a tunable resistance modulation under positive and negative pulse trains, which could fully mimic the potentiation and depression behavior like a bio-synapse. Several synaptic plasticity functions, including long-term potentiation (LTP) and long-term depression (LTD), paired-pulsed facilitation (PPF), spike-rate-dependent-plasticity (SRDP), and post-tetanic potentiation (PTP), are faithfully implemented with the fabricated memristor. Moreover, to demonstrate the feasibility of our memristor synapse for neuromorphic applications, spike-time-dependent plasticity (STDP) is also investigated. Based on conductive atomic force microscopy observations and electrical transport model analyses, it can be concluded that it is the controlled formation and rupture of Ag filaments that are responsible for the resistive switching while exhibiting a switching ratio of ~10 3 along with a good endurance and stability suitable for nonvolatile memory applications. Before fully electroforming, the gradual conductance modulation of Ag/STO:Ag/SiO 2 / p ++ -Si memristor can be realized, and the working mechanism could be explained by the succeeding growth and contraction of Ag filaments promoted by a redox reaction. This newly fabricated memristor may enable the development of nonvolatile memory and realize controllable resistance/weight modulation when applied as an artificial synapse for neuromorphic computing.

Bulk Glassy GeTe2: A Missing Member of the Tetrahedral GeX2 Family and a Precursor for the Next Generation of Phase-Change Materials

Vitreous germanium disulfide GeS2 and diselenide GeSe2 belong to canonical chalcogenide glasses extensively studied over the past half century. Their high-temperature orthorhombic polymorphs are congruently melting compounds, and the tetrahedral crystal and glass structure is largely preserved in the melt. In contrast, the ditelluride counterpart is absent in the Ge–Te phase diagram, which shows only a single compound, monotelluride GeTe. Phase-change materials based on GeTe have become a technologically important class of solids, and their structure and properties are also widely studied. Surprisingly, very scarce information is available for alloys having GeTe2 stoichiometry. Using a fast quenching procedure in silica capillaries, high-energy X-ray diffraction, and Raman spectroscopy supported by first-principles simulations, we show that bulk glassy GeTe2 differs substantially from the lighter GeX2 members, revealing 46% of trigonal germanium, 31% of three-fold coordinated tellurium, and only 20% of edge-sharing tetrahedra or pyramids. The fraction of homopolar Ge–Ge bonds is low; however, the population of dominant Te–Te dimers and Ten oligomers, n ≤ 10, appears to be significant. The complex structural and chemical topology of g-GeTe2 is directly related to the thermodynamic metastability of germanium ditelluride, schematically represented by the following reaction: GeTe2 ⇄ GeTe + Te. Disproportionation is complete above liquidus in the temperature range of semiconductor–metal transition, and the dense metallic GeTe2 liquid, mostly consisting of five-fold coordinated Ge species, exhibits high fluidity, strong fragility (m = 99 ± 5), and presumably a fast structural transformation rate combined with low atomic mobility in the vicinity of the glass transition temperature, favorable for reliable long-term data retention in nonvolatile memories. The observed and predicted characteristic features make GeTe2 a promising precursor for the next generation of phase-change materials, especially coupled with additional metal doping, depolymerizing the tetrahedral interconnected glass network and accelerating (sub)nanosecond crystallization.

Improvement in Long-Term and High-Temperature Retention Stability of Ferroelectric Field-Effect Memory Transistors With Metal–Ferroelectric–Metal–Insulator–Semiconductor Gate-Stacks Using Al-Doped HfO2 Thin Films

Nonvolatile memory characteristics of the ferroelectric field-effect transistors (FeFETs) were investigated by introducing the metal–ferroelectric–metal–insulator–semiconductor (MFMIS) gate-stacks, employing Al-doped HfO2 (Al:HfO2) ferroelectric thin films. The obtained memory window (MW) of the MFMIS FETs increased from 1.0 to 2.8 V by increasing the areal ratios of the metal–insulator–semiconductor (MIS) to the metal–ferroelectric–metal (MFM) (SI/SF) from 8 to 32. The device with an SI/SF ratio of 16 exhibited a 3-order-of-magnitude on/off memory margin even with a program pulse duration of 500 ns. The long-term data retention was also verified by improving the tolerance against the depolarization field by introducing the MFMIS gate-stacks, which can use fully saturated polarization. The temperature-dependent memory performance and operational reliabilities of the MFMIS-FETs were also investigated at high temperatures to exploit fully the thermal stability of the Al:HfO2. The obtained MWs were not markedly degraded for a retention time of 104 s from room temperature (RT) to 80 °C.

A Hive-Based Retrieval Optimization Scheme for Long-Term Storage of Massive Call Detail Records

With the dramatic rise of mobile internet users and the administrative requirements of long-term data retention, telecom providers are facing increasingly challenging storage and retrieval issues of call detail records (CDRs). The existing storage system can only achieve the requirement of online query and offline analysis of the CDRs. However, to the best of our knowledge, few studies have focused on the topic of CDRs retrieval optimization with long-term storage. In order to improve the retrieval speed while ensuring a high compression ratio, in this paper we propose a novel hash storage scheme, termed dual-column bucketing (DCB), based on the Hive platform by making use of its Bucketing nature. Compared to the conventional scheme, the proposed DCB scheme can improve the performance both for CDRs compression and query. Second, similar storage scenarios such as storage of SMS, email and extended detail records (XDRs) are included in the optimization scope of the DCB. Experiments on real-world CDRs show that in contrast to the conventional scheme, the proposed DCB scheme can save the storage space by approximately 40%, reduces the amount of disk read to 2%, and improve the retrieval speed of known phone number queries by up to seven times.

A data-assisted reliability model for carrier-assisted cold data storage systems

Cold data storage systems are used to allow long term digital preservation for institutions’ archive. The common functionality among cold and warm/hot data storage is that the data is stored on some physical medium for read-back at a later time. However in cold storage, write and read operations are not necessarily done in the same exact geographical location. Hence, a third party assistance is typically utilized to bring together the medium and the drive. On the other hand, the reliability modeling of such a decomposed system poses few challenges that do not necessarily exist in other warm/hot storage alternatives such as fault detection and absence of the carrier, all totaling up to the data unavailability issues. In this paper, we propose a generalized non-homogenous Markov model that encompasses the aging of the carriers in order to address the requirements of today’s cold data storage systems in which the data is encoded and spread across multiple nodes for the long-term data retention. We have derived useful lower/upper bounds on the overall system availability. Furthermore, the collected field data is used to estimate parameters of a Weibull distribution to accurately predict the lifetime of the carriers in an example scale-out setting.

Multi-level operation of three-dimensionally stacked non-volatile ferroelectric polymer memory with high-performance hole-injection layer

Abstract Carrier injection from the source electrode to the semiconducting channel in a field-effect transistor (FET) is efficiently enhanced by inserting an interlayer capable of reducing the injection barrier, yielding a device with a greatly increased ON current. In this study, we demonstrated a non-volatile vertical-channel (VC) ferroelectric field effect transistor (FeFET) memory based on ferroelectric polarization switching of a ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) as a gate insulator with a thin MoO3 interlayer. Owing to the facile hole injection through the MoO3 interlayer to a semiconducting channel of the FeFET, the saturated ON current was significantly increased, giving rise to a large ON/OFF memory margin. Optimization of the VC-FeFET thus led to a non-volatile memory operating at a programming voltage of ±25 V with a maximum ON/OFF current margin of 103, reliable time-dependent data retention for more than 1 year, and write/erase endurance for 105 cycles. Furthermore, by sequentially stacking three arrays of VC-FeFETs with the hole-injection interlayers, we fabricated three-dimensionally (3D) stacked VC-FeFETs. Each device had a sufficient ON/OFF current ratio for multi-level memory operation, in which four distinct states were repetitively programmed and erased with long-term data retention and reliable cycle endurance.

Leveraging 3D geometric knowledge in the product lifecycle based on industrial standards

AbstractWith their practical introduction by the 1970s, virtual product data have emerged to a primary technical source of intelligence in manufacturing. Modern organization have since then deployed and continuously improved strategies, methods and tools to feed the individual needs of their business domains, multidisciplinary teams, and supply chain, mastering the growing complexity of virtual product development. As far as product data are concerned, data exchange, 3D visualization, and communication are crucial processes for reusing manufacturing intelligence across lifecycle stages. Research and industry have developed several CAD interoperability, and visualization formats to uphold these product development strategies. Most of them, however, have not yet provided sufficient integration capabilities required for current digital transformation needs, mainly due to their lack of versatility in the multi-domains of the product lifecycle and primary focus on individual product descriptions.This paper analyses the methods and tools used in virtual product development to leverage 3D CAD data in the entire life cycle based on industrial standards. It presents a set of versatile concepts for mastering exchange, aware and unaware visualization and collaboration from single technical packages fit purposely for various domains and disciplines. It introduces a 3D master document utilizing PDF techniques, which fulfills requirements for electronic discovery and enables multi-domain collaboration and long-term data retention for the digital enterprise.Highlights With their practical introduction by the 1970s, virtual product data have emerged to a primary technical source of intelligence in manufacturing. Modern organization have since then deployed and continuously improved strategies, methods and tools to feed the individual needs of their business domains, multidisciplinary teams, and supply chain, mastering the growing complexity of virtual product development. As far as product data are concerned, data exchange, 3D visualization, and communication are crucial processes for reusing manufacturing intelligence across lifecycle stages. Research and industry have developed several CAD interoperability, and visualization formats to uphold these product development strategies. Most of them, however, have not yet provided sufficient integration capabilities required for current digital transformation needs, mainly due to their lack of versatility in the multi-domains of the product lifecycle and primary focus on individual product descriptions. This paper analyses the methods and tools used in virtual product development to leverage 3D CAD data in the entire life cycle. It presents a set of versatile concepts for mastering exchange, aware and unaware visualization and collaboration from single technical packages fit purposely for various domains and disciplines. It introduces a 3D master document utilizing PDF techniques, which fulfills requirements for electronic discovery and enables multi-domain collaboration and long-term data retention for the digital enterprise. 3D interoperability makes an important contribution to engineering collaboration. Several formats made to that end successively deal with challenges of their time. Some of these such as STEP are highly verbose formats, which gradually encapsulate all information necessary to define a product, its manufacture, and lifecycle support. Others are focusing best on lightweight visualization use cases and endure better with increasing size and complexity of data. Traditional formats like STEP and JT, though, are not capable of supporting the publishing activity in even broader fashion. New tendencies therefore are aiming at strengthening these individual formats through combination with complementary standards or by using document-based approaches. Unlike STEP or JT, 3D PDF can serve multiple purposes and leverages 3D data downstream throughout the product lifecycle to create, distribute and manage ubiquitous, highly consumable, role-specific rich renditions. Based on its container structure, 3D PDF is a fundamentally different approach from traditional experience established in product development – it is an exceptionally proficient contextual aggregation of multi-domain and multi-disciplinary product data. The manufacturing community should embrace it as an addition and great improvement to current engineering collaboration standards. All engineering components required for its descriptions are meanwhile published international standards. The productive use of 3D PDF for sure requires a change in the current mode of operation, be it simply because the traditional CAD model promptly demands new technical descriptions. More perspectives, which have not been primary focus of this approach need to be addressed in order to implement the 3D digital master concept of this paper in the industry. For the complete process to work properly, the actual workflows of today's business organizations must succeed a readiness check involving enhanced technical documentation capabilities of the authoring (CAx) applications based on 3D, PLM, and manufacturing workflows as well as new ways for engineering data communication with supply chain partners in the digital enterprise.

A 72% error reduction scheme based on temperature acceleration for long-term data storage applications: Cold flash and millennium memories

A solid-state drive (SSD) with 1Xnm triple-level cell (TLC) NAND flash is proposed for low cost data storage applications with long-term data-retention requirements. Specifically, cold data storage requires 20years data-retention with 100 write/erase (W/E) cycles, whereas digital archive storage requires 1000years retention time with 1 W/E cycle. To achieve these requirements, a flexible-nLC scheme is proposed to improve the reliability of 1Xnm TLC NAND flash (Yamazaki et al., 2015). The proposed scheme combines two schemes, n-out-of-8 level cell (nLC) (Tanakamaru et al., 2014) and asymmetric coding (AC) (Tanakamaru et al., 2012) with the addition of a vertical flag. By measuring 1Xnm TLC NAND flash memory, the proposed scheme reduces errors by 72% and 69% for digital archive and cold flash respectively, compared to the conventional nLC scheme.

Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory

ABSTRACTMetal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2X nm. In this work, metal FG memory device with high-k engineered Inter-Gate-Dielectric (IGD) and/or tunneling layer (TL) was detailed investigated. It presents improved performance with lower operation voltage as well as faster speed, compared to control samples. Furthermore, improvement of long-term data retention is observed for the high-k engineered devices, proving that the introduction of engineered IGD and/or TL is a promising solution for further performance improvement of full metal FG memory device.

Characterization of Low-Dielectric Constant Silicon Carbonitride (SiCN) Dielectric Films for Charge Trapping Nonvolatile Memories

We investigated the charge retention characteristics of the charge-trapping type memory capacitors with blocking oxide-SiCN-tunneling oxide stacked films at four different temperatures. Long-term data retention more than 10 years was estimated at 85 °C for the SiCN memory capacitors. We presented a simple method to analyze the energy distribution of trap states inside the SiCN layer. The trapped electrons were estimated to be distributed from 0.8 to 1.3 eV below the conduction band edge in the SiCN band gap.

Characterization of Low-Dielectric Constant Silicon Carbonitride (SiCN) Dielectric Films for Charge Trapping Nonvolatile Memories

The MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure with a silicon nitride charge trapping layer has received considerable attention for ultra-high density NVM technology. In this architecture, the trapped charge carriers in the charge trapping layer causes a shift in the threshold voltage of memory transistors. However, it is a critical challenge for MONOS-type NVMs to fulfill the requirements of fast programming and erasing speeds and long retention time simultaneously. Recently, we have proposed the application of silicon carbonitride (SiCN) dielectric films with a low-dielectric constant (low-k) to the charge trapping layers [1-6]. The relative dielectric constant of SiCN films is 4.8-4.9, which is lower than that of silicon nitride films (~7). The carrier density in the charge trapping layer which is necessary to induce a fixed threshold voltage shift is a function of the dielectric constant of the charge trapping layer. The necessary carrier density in the SiCN charge trapping layer is low as compared to that in the silicon nitride charge trapping layer. This would result in low power consumption and high programming and erasing speeds in the SiCN-based memory. In the present study, we investigated the charge retention behavior of memory capacitors with the SiCN charge trapping layer and proposed a simple method for analyzing the trap distribution in the SiCN layer. Memory capacitors with blocking oxide-SiCN-tunneling oxide stacked films were fabricated on the silicon substrates. A tunnel oxide film of 2.4 nm in thickness was first formed on p-type (100) silicon substrates using a rapid thermal oxidation technique. A 31.5-nm-thick SiCN film with a relative dielectric constant of 4.8-4.9 was grown at 400 °C using a PECVD technique. A 17.3-nm-thick blocking oxide film was grown using a PECVD technique. Finally, an aluminum film was deposited to form the gate electrode on the SiOX-SiCN-SiO2stacked films. Programming and erasing voltages of +14.3 V and -15.1 V were applied to the gate electrode with grounded the silicon substrate to inject electrons and holes from the substrate into the SiCN layer. Charge retention characteristics of the SiCN memory capacitors in the programming condition were measured at temperatures ranging from room temperature to 235°C. Many trap states were filled by electrons during programming operation. After programming operation and the successive baking at different temperatures, the flat-band voltage in the capacitors was shifted. This shift in the flat-band voltage is mostly due to the emission of trapped electrons from the SiCN layer. Figure 1 shows the charge retention characteristics of the SiCN memory capacitors for four different temperatures. The occupancy function f is defined as the ratio of the density of filled trap states at any retention time t to the density of filled trap states at t=0 s. f was obtained from the flat-band voltage shift. We can see that the emission rates of electrons is thermally activated. Here, assuming that the electron emission is dominated by thermal excitation at higher temperatures, we have calculated the energy distribution of the trapped electrons. As shown in Fig. 2, the energy range of trapped electrons is obtained to be from 1.5 eV to 2.0 eV below the conduction band edge in the SiCN band gap. The results show that the long-term data retention of the SiCN memory capacitor attributed to the presence of energetically deep traps in the SiCN band gap. Hence, the SiCN dielectric films with a low-dielectric constant can be employed as the charge trapping layer of the nonvolatile memories. Acknowledgement: We would like to express gratitude to S. Tanaka, H. Shibayama and J. Nakamura for their valuable discussions. This work was partly supported by a Grant-in-Aid for Scientific Research (No. 26420280) from JSPS.