Logic States Research Articles

A many-body quantum register for a spin qubit

Abstract Quantum networks require quantum nodes with coherent optical interfaces and several stationary qubits. In terms of optical properties, semiconductor quantum dots are highly compelling, but their adoption as quantum nodes has been impaired by the lack of auxiliary qubits. Here we demonstrate that the dense, always-present, nuclear spin ensemble surrounding a gallium arsenide quantum dot can be used as a functional quantum register. We prepared 13,000 host nuclear spins in a single many-body dark state that acts as a logical state of the register. A second logical state is defined as a single nuclear-magnon excitation, enabling controlled quantum-state transfer between an electron spin qubit in the quantum dot and the nuclear magnonic register. Using SWAP gates, we implemented a full write–store–retrieve-read-out protocol with 68.6(4)% raw overall fidelity and a storage time of 130(16) μs, which could be extended to 20 ms or beyond using dynamical decoupling techniques. Our work establishes how many-body physics can add functionality to quantum devices, in this case transforming quantum dots into multi-qubit quantum nodes with deterministic registers.

Mixed-Dimensional Semiconductors-Based Ternary Circuits with Tunable Negative Transconductance Characteristics.

Multivalued logic (MVL) systems, in which data are processed with more than two logic values, are considered a viable solution for achieving superior processing efficiency with higher data density and less complicated system complexity without further scaling challenges. Such MVL systems have been conceptually realized by using negative transconductance (NTC) devices whose channels consist of van der Waals (vdW) heterojunctions of low-dimensional semiconductors; however, their circuit operations have not been quite ideal for driving multiple stages in real circuit applications due to reasons such as a reduced output swing and poorly defined logic states. Herein, we demonstrate ternary inverter circuits with near rail-to-rail swing and three distinct logic states by employing vdW p-n heterojunctions of single-walled carbon nanotubes (SWCNT) and MoS2 where the SWCNT layer completely covers the MoS2 layer. In particular, SWCNTs are inkjet printed to form heterojunctions with MoS2 grown by chemical vapor deposition (CVD), and both inkjet printing and CVD are fully scalable device fabrication methods for low-dimensional materials. In addition, the NTC characteristics of heterojunction field-effect transistors (H-FETs) are explained based on the electrical characteristics of individual SWCNT and MoS2 channels. By adjustment of the p-channel characteristics in H-FETs by exploiting the advantages of the inkjet printing technology, the widths of the NTC regions are easily adjusted accordingly. The extended NTC region enables stable middle logic state operations of low-dimensional semiconductors-based ternary inverters over a sufficiently wide input voltage range.

Ternary Logic Transistors Using Multi-Stacked 2D Electron Gas Channels in Ultrathin Oxide Heterostructures.

2D electron gas field-effect transistors (2DEG-FETs), employing 2DEG formed at an interface of ultrathin (≈6nm) Al2O3/ZnO heterostructure as the active channel, exhibit outstanding drive current (≈215µA), subthreshold swing (≈132mV dec-1), and field effect mobility (≈49.6 cm2V-1 s-1) with a high on/off current ratio of ≈107. It is demonstrated that the Al2O3 upper layer in Al2O3/ZnO heterostructure acts as the source/drain resistance component during transistor operations, and the applied potential to the 2DEG channel is successfully modulated by Al2O3 thickness variations so that the threshold voltage (Vth) is effectively tuned. Remarkably, double-stacked 2DEG-FETs consisting of two Al2O3/ZnO heterostructured 2DEG channels with a single gate exhibit multiple Vth, enabling a ternary logic state in a single device. By inducing a voltage difference between the stacked channels, a sequential operation of the upper and lower FETs is achieved, successfully realizing a stable ternary logic operation.

Numerical analysis of All-Optical universal NAND and NOR photonic crystal logic gates by creating holes in silicon material

All-optical NAND and NOR logical gates based on two-dimensional photonic crystals have been designed and analyzed in this research. A hole in the silicon substrate was created to design the desired gates, and the light emission analysis was performed using the FDTD numerical method. Most of the circuits that have been designed so far based on photonic crystals have included dielectric rods in the airfield. This research uses a hole in the silicon substrate, which is more suitable for fabrication. The proposed structure is created symmetrically using a small photonic crystal. The simulation results show that this small structure can be used as two NAND and NOR gates, which have a suitable power difference in the upper and lower logic states. Therefore, the proposed structure is suitable for precise logic circuits and high transmission speed. Due to the simplicity of structure and small size, the output stable time for NAND and NOR gates are 0.9 ps and 0.67 ps, respectively, indicating the gates’ low delay time. Also, the value of the contrast ratio for NAND and NOR gates is 7.26 dB and 6.35 dB, respectively, which indicates the appropriate power difference in the upper and lower logic states.

Institutional Complexity and Social Innovation: The Case of Chinese Social Enterprises

Abstract Social enterprises (SEs) have emerged throughout the world to address societal challenges through market-based activities and innovation. Research has focused on how SEs manage the tensions arising from the combination of social-welfare and market logics, neglecting the institutional complexity that arises in authoritarian regimes where the state plays a dominant role. Based on the institutional logics perspective and interview data of 42 SE leaders in China, we find that key tensions arise from the state and social-welfare logics and that state logic (re)configures the social–market relationships to be compatible. Chinese SEs employed depoliticization and localization to adapt to this unique form of institutional complexity in their social innovation efforts. This study advances research on SEs, institutional complexity, and hybrid organizing.

Comparing Shor and Steane error correction using the Bacon-Shor code.

Quantum states decohere through interaction with the environment. Quantum error correction can preserve coherence through active feedback wherein quantum information is encoded into a logical state with a high degree of symmetry. Perturbations are detected by measuring the symmetries of the state and corrected by applying gates based on these measurements. To measure the symmetries without perturbing the data, ancillary quantum states are required. Shor error correction uses a separate quantum state for the measurement of each symmetry. Steane error correction maps the perturbations onto a logical ancilla qubit, which is then measured to check several symmetries simultaneously. We experimentally compare Shor and Steane correction of bit flip errors using the Bacon-Shor code implemented in a chain of 23 trapped atomic ions. We find that the Steane method produces fewer errors after a single round of error correction and less disturbance to the data qubits without error correction.

Institutional pluralism, accounting and the state: The Opera del Duomo in Pisa as a hybrid organisation (XI–XVI centuries)

This study considers the Opera del Duomo in Pisa, the organisation tasked with building the world-renowned complex located in the Square of Miracles, from its inception to the formation of the Grand Duchy of Tuscany in the sixteenth century. It draws upon Besharov and Smith's understanding of hybridity to document the factors driving the transition from a form of hybridity characterised by a high level of conflict between the logics of the State, the Church and the Commune of Pisa to a form in which the State logic dominated over the others and conflict was overcome. The article unveils how the regulatory power of the State generates changes in the interactions among logics over time, with particular attention to the role of accounting and accountability practices. It shows how historical studies help to untangle situations in which logics coexist in extreme conflict and identify new ways to engage with them.

Gate control of superconducting current: Mechanisms, parameters, and technological potential

In conventional metal-oxide semiconductor (CMOS) electronics, the logic state of a device is set by a gate voltage (VG). The superconducting equivalent of such effect had remained unknown until it was recently shown that a VG can tune the superconducting current (supercurrent) flowing through a nanoconstriction in a superconductor. This gate-controlled supercurrent (GCS) can lead to superconducting logics like CMOS logics, but with lower energy dissipation. The physical mechanism underlying the GCS, however, remains under debate. In this review article, we illustrate the main mechanisms proposed for the GCS, and the material and device parameters that mostly affect it based on the evidence reported. We conclude that different mechanisms are at play in the different studies reported so far. We then outline studies that can help answer open questions on the effect and achieve control over it, which is key for applications. We finally give insights into the impact that the GCS can have toward high-performance computing with low-energy dissipation and quantum technologies.

Research Data Management in German Academia from a Multiple Logic Perspective

The requirements for research data management (RDM) have increased. Due to academia’s neoliberalization, however, researchers already face a high workload within a hypercompetitive environment. The demand to integrate RDM as an additional task into academics’ day-today actions seems to be quixotic. To deepen our understanding of early career researchers’ (ECRs) daily work arbitrage, we need to know more about their behavior, actions, and decisions in relation to RDM. Drawing on a multiple institutional logics perspective at the micro-level, we conducted 40 semistructured interviews at German higher education institutions (HEIs) to investigate how ECRs respond to institutional logics in the context of RDM. Our findings revealed three profiles – the conformist, the waverer, and the resister – that make use of different response strategies to the state, market, professional, and community logic. We contribute to institutional logic research at the micro-level and, in addition, broaden prior research on HEIs and RDM by taking neoliberal academia into account.

Institutional logics and organizational green transformation: Evidence from the agricultural industry in emerging economies

While the agricultural green transformation has garnered significant attention on the political stage as a crucial strategy for climate change mitigation and sustainable development, there remains a notable gap in our understanding of the prevailing logics that shape organizational decisions on this change in emerging economies. Drawing on the institutional logics perspective, this study explores the impact of state logic (manifested through green credit policy) and market logic (manifested through analyst attention) on agriculture-related firms' (ARFs') green transformation, as well as the moderating effects of organizational transparency and environmental, social, and governance (ESG) level. Using longitudinal data on 201 publicly listed ARFs in China from 2008 to 2020, we find that both state and market logics exert unique effects on facilitating the green transformation of ARFs. More notably, a complementarity between the two logics in offering value for ARFs’ green transformation is revealed. This complementary effect becomes more pronounced for organizations with a higher level of transparency or a superior ESG profile. Our study contributes to the neo-institutional perspective of organizational green transformation, a better understanding of conflicting institutional logics in emerging economies, and research on agricultural sustainability.

Investigation of the TaOx unipolar switching memory on high efficiency computing

Memristor has shown great potential application for data storage, neuromorphic computing chip, and memory logic, but its bi-directional operation from setting in positive bias voltage region to resetting in a negative bias voltage region would introduce a complex control circuit. Herein, a memristor with the structure of Au/TaOx/F-doped SnO2 presents unipolar switching behavior, enabling the memristor to operate the set and reset processing in a single voltage direction. By comparison with bipolar switching memristor, using this unipolar switching memristor to operate the logic expression of the letter “D” based on American standard code for information interchange (ASCII) can reduce power consumption by 55.56 % while switching the logic state from “0” to “1” and then back to “0” can save up to 48 % of power consumption. This work provides a feasible method for the low power consumption computing as well as a road to simplify circuit design.

Reducing the error rate of a superconducting logical qubit using analog readout information

Quantum error correction enables the preservation of logical qubits with a lower logical error rate than the physical error rate, with performance depending on the decoding method. Traditional decoding approaches rely on the binarization (“hardening”) of readout data, thereby ignoring valuable information embedded in the analog (“soft”) readout signal. We present experimental results showcasing the advantages of incorporating soft information into the decoding process of a distance-3 (d=3) bit-flip surface code with flux-tunable transmons. We encode each of the 16 computational states that make up the logical state |0L⟩, and protect them against bit-flip errors by performing repeated Z-basis stabilizer measurements. To infer the logical fidelity for the |0L⟩ state, we average across the 16 computational states and employ two decoding strategies: minimum-weight perfect matching and a recurrent neural network. Our results show a reduction of up to 6.8% in the extracted logical error rate with the use of soft information. Decoding with soft information is widely applicable, independent of the physical qubit platform, and could allow for shorter readout durations, further minimizing logical error rates. Published by the American Physical Society 2024

DOBRE PRAKTYKI HYBRYDOWYCH SPÓŁEK SKARBU PAŃSTWA NOTOWANYCH NA GPW W WARSZAWIE

State-owned enterprises play a major role in today's global economy. However, they are accused of low efficiency as a result of flawed corporate governance. Listed state-owned enterprises are hybrid companies because they combine different institutional logics. Listed companies, in order to gain legitimacy from stakeholders, provide information to the market. Stakeholders expect companies to provide reliable information on the achievement of goals they care about. Corporate governance is monitored on reports of listed companies' adherence to good practices of listed companies. It was decided to investigate the usefulness for stakeholders of reports on compliance with the good practice of companies on the Warsaw Stock Exchange for assessing corporate governance. Corporate governance is a problem for state-owned enterprises due to the need to combine corporate and state logic. Hybrid state-owned enterprises (SOEs) also have to follow the logic of the capital market. Therefore, the subject of the study was compliance with good practices of listed companies by hybrid SOEs listed on the Warsaw Stock Exchange. The aim of the study was to find out how their corporate governance compares with other companies. A quantitative study was conducted using the COMPLY factor. It turned out that hybrid SOEs performed better than other companies listed on the same stock indices and in the same sectors. Thus, the results of the study point to the inadequacy of the good practice reporting system.

Optimization of Decoder Priors for Accurate Quantum Error Correction.

Accurate decoding of quantum error-correcting codes is a crucial ingredient in protecting quantum information from decoherence. It requires characterizing the error channels corrupting the logical quantum state and providing this information as a prior to the decoder. We introduce a reinforcement learning inspired method for calibrating these priors that aims to minimize the logical error rate. Our method significantly improves the decoding accuracy in repetition and surface code memory experiments executed on Google's Sycamore processor, outperforming the leading decoder-agnostic method by 16% and 3.3%, respectively. This calibration approach will serve as an important tool for maximizing the performance of both near-term and future error-corrected quantum devices.

Core-shell architecture and channel suppression: unleashing the potential of SC_RCS_DGJLFET

In this investigation, a suppressed channel-rectangular core–shell double gate junctionless field effect transistor (SC_RCS_DGJLFET) is simulated to enhance the junctionless device’s performance. This study leverages a core–shell architecture and channel suppression technique to improve the gate controllability over the channel region which helps in substantial depletion of the shells in the OFF state of the device. When compared to conventional double gate JLFETs (C_DGJLFET) and rectangular core–shell double gate JLFETs (RCS_DGJLFET), the performance of the SC_RCS_DGJLFET is superior in terms of IOFF, ION/IOFF ratio, DIBL and subthreshold slope (SS). The SC_RCS_DGJLFET achieves an ultra-low IOFF of 7.033 × 10−16 A, indicating a low leakage current with an impressive ION/IOFF = 5.092 × 1011 . Other performance parameters such as subthreshold slope and DIBL has also been improved for the SC_RCS_DGJLFET device. Subthreshold slope has been decresesd by 4.76% whereas the DIBL decreased by 33.82% when compared to existing RCS_DGJLFET. Additionally, to analyze the effect of doping on the device performance, the core doping in SC_RCS_DGJLFET is varied for fixed shell doping. The study found that fixing core doping to an appropriate value is a crucial parameter to achieve good device performance. The impact of variation of oxide extension towards the source and drain LextS/LextD in SC_RCS_DGJLFET is also studied for the first time in the core–shell architecture which has further improved the device’s performance. Finally, a CMOS inverter is designed using the proposed device that provides valuable insights into its suitability for digital circuit applications and verifies its performance benefits compared to existing transistor technologies. The SC_RCS_DGJLFET based CMOS inverter shows a sharp transition in voltage transfer characteristics (VTC), indicating fast switching speed and precise signal processing capabilities when compared to a CMOS inverter based on a conventional double gate junctionless field effect transistor (C_DGJLFET). Moreover, the transient characteristics of the SC_RCS_DGJLFET based CMOS inverter exhibit an improved output voltage swing, suggesting enhanced dynamic behaviour and stability during logic state transitions.

Realization of ultra-compact and high contrast ratio all-optical 4-to-2 encoder based on 2D photonic crystals

Optical encoders are widely used circuits in digital systems. One of the most critical features of an optical encoder is the power values in two logic states; low and high. The difference between these two values is expressed with the contrast ratio (CR) parameter. This research has designed and simulated an optical encoder based on a two-dimensional (2D) photonic crystal with four inputs and two outputs. The results show that the proposed structure has low power in low mode and high intensity in high mode. This difference in two logical modes has caused the proposed encoder to have CR = 19.8 dB, which is improved compared to previous works. Also, the proposed structure is very compact and its footprint is as small as 96.88 µm2. The data speed for the designed encoder is BR=2Tb/s\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$BR = 2{\ ext{ Tb/s}}$$\\end{document}. This encoder can be used in high-speed optical integrated circuits with low error according to the obtained values.

A hot-emitter transistor based on stimulated emission of heated carriers

Hot-carrier transistors are a class of devices that leverage the excess kinetic energy of carriers. Unlike regular transistors, which rely on steady-state carrier transport, hot-carrier transistors modulate carriers to high-energy states, resulting in enhanced device speed and functionality. These characteristics are essential for applications that demand rapid switching and high-frequency operations, such as advanced telecommunications and cutting-edge computing technologies1–5. However, the traditional mechanisms of hot-carrier generation are either carrier injection6–11 or acceleration12,13, which limit device performance in terms of power consumption and negative differential resistance14–17. Mixed-dimensional devices, which combine bulk and low-dimensional materials, can offer different mechanisms for hot-carrier generation by leveraging the diverse potential barriers formed by energy-band combinations18–21. Here we report a hot-emitter transistor based on double mixed-dimensional graphene/germanium Schottky junctions that uses stimulated emission of heated carriers to achieve a subthreshold swing lower than 1 millivolt per decade beyond the Boltzmann limit and a negative differential resistance with a peak-to-valley current ratio greater than 100 at room temperature. Multi-valued logic with a high inverter gain and reconfigurable logic states are further demonstrated. This work reports a multifunctional hot-emitter transistor with significant potential for low-power and negative-differential-resistance applications, marking a promising advancement for the post-Moore era.

Design of All-Optical D Flip Flop Memory Unit Based on Photonic Crystal.

This paper proposes a unique configuration for an all-optical D Flip Flop (D-FF) utilizing a quasi-square ring resonator (RR) and T-Splitter, as well as NOT and OR logic gates within a 2-dimensional square lattice photonic crystal (PC) structure. The components realizing the all-optical D-FF comprise of optical waveguides in a 2D square lattice PC of 45 × 23 silicon (Si) rods in a silica (SiO2) substrate. The utilization of these specific materials has facilitated the fabrication process of the design, diverging from alternative approaches that employ an air substrate, a method inherently unattainable in fabrication. The configuration underwent examination and simulation utilizing both plane-wave expansion (PWE) and finite-difference time-domain (FDTD) methodologies. The simulation outcomes demonstrate that the designed waveguides and RR effectively execute the operational principles of the D-FF by guiding light as intended. The suggested configuration holds promise as a logic block within all-optical arithmetic logic units (ALUs) designed for digital computing optical circuits. The design underwent optimization for operation within the C-band spectrum, particularly at 1550 nm. The outcomes reveal a distinct differentiation between logic states '1' and '0', enhancing robust decision-making on the receiver side and minimizing logic errors in the photonic decision circuit. The D-FF displays a contrast ratio (CR) of 4.77 dB, a stabilization time of 0.66 psec, and a footprint of 21 μm × 12 μm.

Design and implementation of software modularization in T-type three-level inverter

Abstract This paper addresses the issues of logical allocation state constraints, invalid state switching, and program redundancy in the software design process of the signal processor in the T-type three-level inverter. It combines the importance and advantages of modular thinking in software design to propose a solution method for software modularization based on functional analysis and hierarchical module division. The article presents simulation tests and experimental results of the software modularization of the T-type three-level inverter implemented based on FPGA/CPLD chips, validating the feasibility and effectiveness of this design approach.

Robust and Deterministic Preparation of Bosonic Logical States in a Trapped Ion.

Encoding logical qubits in bosonic modes provides a potentially hardware-efficient implementation of fault-tolerant quantum information processing. Here, we demonstrate high-fidelity and deterministic preparation of highly nonclassical bosonic states in the mechanical motion of a trapped ion. Our approach implements error-suppressing pulses through optimized dynamical modulation of laser-driven spin-motion interactions to generate the target state in a single step. We demonstrate logical fidelities for the Gottesman-Kitaev-Preskill state as high as F[over ¯]=0.940(8), a distance-3 binomial state with an average fidelity of F=0.807(7), and a 12.91(5)dB squeezed vacuum state.