Logic Density Research Articles

Multibarrier Collaborative Modulation Devices with Ultra-High Logic Operation Density.

The demands for highly miniaturized and multifunctional electronics are rapidly increasing. As scaling-down processes of transistors are restricted by physical limits, reconfigurable electronics with switchable operation functions for different tasks are developed for higher function integration based on split- or vertical-dual-gate structures. To promote the present reconfigurable electronics and exceed the function integration limit, the critical issue is to integrate complex operations into simple circuit forms by establishing more control dimensions. This work proposes a multibarrier collaborative (MBC) modulation architecture to increase the control dimension by multiple forms of potential barriers and achieves combinational and reconfigurable logic operations by a single MBC device. The MBC architecture exhibits ultrahigh logic operation density, including 58.8% area reduction for multiplexer operations and 71.4% area reduction for 4-logic reconfigurable operations. Besides, a hardware security module composed of 4 MBC devices implementing 8 types of logic operations is demonstrated. This work reveals an effective design of function integration for next-generation electronics.

Overcoming the High Error Rate of Composite DNA Letters-Based Digital Storage through Soft-Decision Decoding.

Composite DNA letters, by merging all four DNA nucleotides in specified ratios, offer a pathway to substantially increase the logical density of DNA digital storage (DDS) systems. However, these letters are susceptible to nucleotide errors and sampling bias, leading to a high letter error rate, which complicates precise data retrieval and augments reading expenses. To address this, Derrick-cp is introduced as an innovative soft-decision decoding algorithm tailored for DDS utilizing composite letters. Derrick-cp capitalizes on the distinctive error sensitivities among letters to accurately predict and rectify letter errors, thus enhancing the error-correcting performance of Reed-Solomon codes beyond traditional hard-decision decoding limits. Through comparative analyses in the existing dataset and simulated experiments, Derrick-cp's superiority is validated, notably halving the sequencing depth requirement and slashing costs by up to 22% against conventional hard-decision strategies. This advancement signals Derrick-cp's significant role in elevating both the precision and cost-efficiency of composite letter-based DDS.

Laser writing of memristive logic gates and crossbar arrays

Memristor-based logic circuits are gaining a lot of attention due to the potential for high logic density hardware and novel in-memory computing applications. Readily available methods for fabricating of memristor logic structures that are suitable for integration with conventional computer hardware are a growing need. This work presents a direct laser writing process capable of rapidly fabricating memristor logic circuits by laser irradiation of metal salt precursor solutions. Planar memristor patterns are fabricated, and their I–V response is characterized. Boolean logic gates are fabricated from planar memristor pairs that exhibit low programming voltages and rapid switching. Cu/Cu2O/Cu and Ag/Cu2O/Cu memristors are also fabricated in crossbar arrays, showing the ability to be programmed to multiple resistance states through ultrashort voltage pulses. The devices also show the potential to have high endurance and nonvolatile resistance state retention.

Efficient DNA-based data storage using shortmer combinatorial encoding

Data storage in DNA has recently emerged as a promising archival solution, offering space-efficient and long-lasting digital storage solutions. Recent studies suggest leveraging the inherent redundancy of synthesis and sequencing technologies by using composite DNA alphabets. A major challenge of this approach involves the noisy inference process, obstructing large composite alphabets. This paper introduces a novel approach for DNA-based data storage, offering, in some implementations, a 6.5-fold increase in logical density over standard DNA-based storage systems, with near-zero reconstruction error. Combinatorial DNA encoding uses a set of clearly distinguishable DNA shortmers to construct large combinatorial alphabets, where each letter consists of a subset of shortmers. We formally define various combinatorial encoding schemes and investigate their theoretical properties. These include information density and reconstruction probabilities, as well as required synthesis and sequencing multiplicities. We then propose an end-to-end design for a combinatorial DNA-based data storage system, including encoding schemes, two-dimensional (2D) error correction codes, and reconstruction algorithms, under different error regimes. We performed simulations and show, for example, that the use of 2D Reed-Solomon error correction has significantly improved reconstruction rates. We validated our approach by constructing two combinatorial sequences using Gibson assembly, imitating a 4-cycle combinatorial synthesis process. We confirmed the successful reconstruction, and established the robustness of our approach for different error types. Subsampling experiments supported the important role of sampling rate and its effect on the overall performance. Our work demonstrates the potential of combinatorial shortmer encoding for DNA-based data storage and describes some theoretical research questions and technical challenges. Combining combinatorial principles with error-correcting strategies, and investing in the development of DNA synthesis technologies that efficiently support combinatorial synthesis, can pave the way to efficient, error-resilient DNA-based storage solutions.

Control-gate-free reconfigurable transistor based on 2D MoTe2 with asymmetric gating

As transistor footprint scales down to the sub-10 nm regime, the process development for advancing to further technology nodes has encountered slowdowns. Achieving greater functionality within a single chip requires concurrent development at the device, circuit, and system levels. Reconfigurable transistors possess the capability to transform into both n-type and p-type transistors dynamically during operation. This transistor-level reconfigurability enables field-programmable logic circuits with fewer components compared to conventional circuits. However, the reconfigurability requires additional polarity control gates in the transistor and potentially impairs the gain from a smaller footprint. In this paper, we demonstrate a 2D control-gate-free reconfigurable transistor based on direct modulation of out-of-plane conduction in an ambipolar MoTe2 channel. Asymmetric electrostatic gating at the source and drain contacts is employed in the MoTe2 transistor resulting in different Schottky barrier widths at the two contacts. Consequently, the ambipolar conduction is reduced to unipolar conduction, where the current flow direction determines the preferred carrier type and the transistor polarity. Temperature dependence of the transfer characteristics reveals the Schottky barrier-controlled conduction and confirms that the Schottky barrier widths at the top contact are effectively tuned by electrostatic gating. Without the complexity overhead from polarity control gates, control-gate-free reconfigurable transistors promise higher logic density and lower cost in future integrated circuits.

High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller

High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller

Lookup Table Merging for FPGA Technology Mapping

Higher logic density is a key goal pursued by Field Programmable Gate Arrays (FPGA). The higher the logic density is, the lower the cost of the circuit spends, and the shorter the line length of the circuit is, the less power is required. Technology mapping is used to map technology-independent logic gates into a lookup table (LUT) netlist. A big problem with the 6-input LUT used in the FPAG at the present stage is that the utilization rate of the lookup table is insufficient. Modern FPGA architectures have good support for dual-output LUTs. We can merge two small LUTs into a new dual-output LUT, if the total number of inputs of the two small LUTs is not greater than the input limit specified by the LUT, thereby reducing the area, that is, reducing the number of LUTs. In this paper, the dual-output LUTs are merged in the technology mapping stage, and a new method of merging single-output LUTs into dual-output LUTs is proposed. The experimental results show that the algorithm used in this paper has an average reduction of 10.21 % in the number of LUTs without worsening delay.

Scaling logical density of DNA storage with enzymatically-ligated composite motifs

DNA is a promising candidate for long-term data storage due to its high density and endurance. The key challenge in DNA storage today is the cost of synthesis. In this work, we propose composite motifs, a framework that uses a mixture of prefabricated motifs as building blocks to reduce synthesis cost by scaling logical density. To write data, we introduce Bridge Oligonucleotide Assembly, an enzymatic ligation technique for synthesizing oligos based on composite motifs. To sequence data, we introduce Direct Oligonucleotide Sequencing, a nanopore-based technique to sequence short oligos, eliminating common preparatory steps like DNA assembly, amplification and end-prep. To decode data, we introduce Motif-Search, a novel consensus caller that provides accurate reconstruction despite synthesis and sequencing errors. Using the proposed methods, we present an end-to-end experiment where we store the text “HelloWorld” at a logical density of 84 bits/cycle (14–42× improvement over state-of-the-art).

A Robust and Efficient DNA Storage Architecture Based on Modulation Encoding and Decoding.

Synthetic DNA has been widely considered an attractive medium for digital data storage. However, the random insertion-deletion-substitution (IDS) errors in the sequenced reads still remain a critical challenge to reliable data recovery. Motivated by the modulation technique in the communication field, we propose a new DNA storage architecture to solve this problem. The main idea is that all binary data are modulated into DNA sequences with the same AT/GC patterns, which facilitate the detection of indels in noisy reads. The modulation signal could not only satisfy the encoding constraints but also serve as prior information to detect the potential positions of errors. Experiments on simulation and real data sets demonstrate that modulation encoding provides a simple way to comply with biological constraints for sequence encoding (i.e., balanced GC content and avoiding homopolymers). Furthermore, modulation decoding is highly efficient and extremely robust, which can correct up to ∼40% of errors. In addition, it is robust to imperfect clustering reconstruction, which is very common in practice. Although our method has a relatively low logical density of 1.0 bits/nt, its high robustness may provide a wide space for developing low-cost synthetic technologies. We believe this new architecture may boost the early coming of large-scale DNA storage applications in the future.

Superconducting pulse conserving logic and Josephson-SRAM

Superconducting digital pulse-conserving logic and Josephson static random access memory (JSRAM) memory together enable scalable circuits with energy efficiency 100× beyond leading-node CMOS. Circuit designs support high throughput and low latency when implemented in an advanced fabrication stack with high-critical-current-density Josephson junctions of 1000 μA/μm2. Pulse-conserving logic produces one single-flux-quantum output for each input and includes a three-input, three-output gate producing logical or3, majority3, and and3. Gate macros using dual-rail data encoding eliminate inversion latency and produce efficient implementations of all standard logic functions. A full adder using 70 Josephson junctions has a carry-out latency of 5 ps corresponding to an effective 12 levels of logic at 30 GHz. JSRAM memory uses single-flux-quantum signals throughout an active array to achieve throughput at the same clock rate as the logic. The unit cell has eight Josephson junctions, a signal propagation latency of 1 ps, and a footprint of 2 μm2. Projected density of JSRAM is 4 MB/cm2, and computational density of pulse-conserving logic is on par with leading node CMOS accounting for power densities and clock rates.

A High-Logic-Density, Low-Power Control Character Detection and Identification Circuit for the JESD204B Data Link Layer

In this brief a design methodology is proposed for the control character detection and identification (CCDI) in JESD204B data link layer. The longest common sequence (LCS) is extracted as the basis in the pre-detection step, and the remaining characteristic sequence is used in the second detection step. The verification results illustrate that the proposed optimization design can achieve high logic density and low power consumption. The reduction of the hardware resources and power consumption is about 37.5% and 17%–20% respectively as compared with the traditional scheme.

Technology Prospects for Data-Intensive Computing

For many decades, progress in computing hardware has been closely associated with CMOS logic density, performance, and cost. As such, slowdown in 2-D scaling, frequency saturation in CPUs, and increased cost of design and chip fabrication for advanced technology nodes since the early 2000s have led to concerns about how semiconductor technology may evolve in the future. However, the last two decades have also witnessed a parallel development in the application landscape: the advent of big data and consequent rise of data-intensive computing, using techniques such as machine learning. In this article, we advance the idea that data-intensive computing would further cement semiconductor technology as a foundational technology with multidimensional pathways for growth. Continued progress of semiconductor technology in this new context would require the adoption of a system-centric perspective to holistically harness logic, memory, and packaging resources. After examining the performance metrics for data-intensive computing, we present the historical trends for general-purpose graphics processing unit (GPGPU) as a representative data-intensive computing hardware. Thereon, we estimate the values of the key data-intensive computing parameters for the next decade, and our projections may serve as a precursor for a dedicated technology roadmap. By analyzing the compiled data, we identify and discuss specific opportunities and challenges for data-intensive computing hardware technology.

Robust data storage in DNA by de Bruijn graph-based de novo strand assembly

DNA data storage is a rapidly developing technology with great potential due to its high density, long-term durability, and low maintenance cost. The major technical challenges include various errors, such as strand breaks, rearrangements, and indels that frequently arise during DNA synthesis, amplification, sequencing, and preservation. In this study, a de novo strand assembly algorithm (DBGPS) is developed using de Bruijn graph and greedy path search to meet these challenges. DBGPS shows substantial advantages in handling DNA breaks, rearrangements, and indels. The robustness of DBGPS is demonstrated by accelerated aging, multiple independent data retrievals, deep error-prone PCR, and large-scale simulations. Remarkably, 6.8 MB of data is accurately recovered from a severely corrupted sample that has been treated at 70 °C for 70 days. With DBGPS, we are able to achieve a logical density of 1.30 bits/cycle and a physical density of 295 PB/g.

Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation

Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> logic density, 1.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> energy efficiency, and 1.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration.

The Tangerine project: Development of high-resolution 65 nm silicon MAPS

The Tangerine project aims to develop new state-of-the-art high-precision silicon detectors. Part of the project has the goal of developing a monolithic active pixel sensor using a novel 65 nm CMOS imaging process, with a small collection electrode. This is the first application of this process in particle physics, and it is of great interest as it allows for an increased logic density and reduced power consumption and material budget compared to other processes. The process is envisioned to be used in for example the next ALICE inner tracker upgrade, and in experiments at the electron-ion collider.The initial goal of the three-year Tangerine project is to develop and test a sensor in a 65 nm CMOS imaging process that can be used in test beam telescopes at DESY, providing excellent spatial resolution and high time resolution, and thus demonstrating the capabilities of the process. The project covers all aspects of sensor R&D, from electronics and sensor design using simulations, to prototype test chip characterisation in labs and at test beams. The sensor design simulations are performed by using a powerful combination of detailed electric field simulations using technology computer-aided design and high-statistics Monte Carlo simulations using the Allpix2 framework. A first prototype test chip in the process has been designed and produced, and successfully operated and tested both in labs and at test beams.

Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs

Switch block flexibility is an important design metric in FPGA architectural research. A switch block with high flexibility can provide better routability for implementing digital applications, which can lead to better performance and logic density. Flexibility, however, does come at the cost of an increase in the layout area of switch blocks, which can lower performance and logic density. Consequently, it is important to accurately estimate the layout area of increasing switch block flexibility in order to better design FPGA architectures. This work focuses on the popular disjoint switch block design and evaluates the accuracy of the traditional active-based area estimation models based on realistic layouts. We found that the current active-based area models are inaccurate in estimating the true area cost of increasing switch block flexibility. This inaccuracy is due to the inability of the current models to consider the full effect of routing track count and wire segment length, two important flexibility parameters, on the layout area of switch blocks. We found that by including wiring area into the estimation of FPGA switch block layout area, one can significantly improve the accuracy of predicting the true area cost of these flexibility parameters. These results allow FPGA architects to better optimize future FPGA designs for routability and consequently for performance and logic density.

A Self-Adaptive SEU Mitigation Scheme for Embedded Systems in Extreme Radiation Environments

When electronic systems are working in radiation environments, transient errors, and permanent errors may occur. Static random-access memory (SRAM) has been the one of most significant parts in various semiconductor chips for its high performance and high logic density features. However, because of their dedicated electronic circuits, SRAMs are sensitive to radiation effects. In this article, a portable scheme combined with error correcting code (ECC) and refreshing techniques is proposed to correct errors and mitigate error accumulation in extreme radiation environments. Since the proposed scheme is small and transparent to other modules and no additional latency is introduced, it therefore can be easily applied to the system where the hardware modules are designed with fixed reading and writing latency. We evaluated this design by simulation in a hardware fault injection platform and radiation experiments in the neutron radiation facility. The results obtained in the neutron experiment, where the flux of neutron particles is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$5 \times {\rm 10^6\text{ cm}^2. \ s^{-1}}$</tex-math></inline-formula> , show that the number of bit-flips in 32 kB self-refresh ECC RAM on the Xilinx Artix-7 FPGA remains zero, while the number of bit-flips in unhardened RAM rose to 32 in 1.5 h.

Silicon Die Transient Thermal Peak Prediction Approach

It is well known that Field Programmable Gate Arrays (FPGA) are good platforms for implementing embedded systems because of their configurable nature. However, the temperature of FPGAs is becoming a serious concern. Improvements in manufacturing technology led to increased logic density in integrated circuits as well as higher clock frequencies. As logic density increases, so do power density, which in turn increases the temperature, FPGAs follow the same path. A prediction of the thermal state of the Altera Cyclone V System-on-Chip (SoC) is presented in this work. The prediction study employs a numerical technique called Finite Element Method (FEM), which is a discretization method to approximate the real solution of the Partial Differential Equation (PDE) for heat transfer around the board's critical sources. The DE1 5CSEMA5F31C6N board was simulated using the COMSOL Multiphysics® tool for predicting thermal peaks during 13 hours of normal operation. Using the NISA tool, we obtained very similar results to those previously obtained with a margin of error of 2 %. As a result, a Verilog code implementation that describes the same approach used by the last two simulation tools is uploaded to the FPGA to verify the results of these simulations. This paper provides a more accurate vision of the level of operating stability of our FPGA board, which are currently the most important source for prototyping and designing the world's largest systems.

HD-Code: End-to-End High Density Code for DNA Storage.

With the rapid development of digital information techniques, the use of DNA media for information storage is considered as the future direction of data storage. Existing DNA storage schemes simply map compressed binary multimedia data into DNA base data, which has the disadvantages of data loss, low logical storage density and high cost of synthesis. This paper presents an end-to-end high density DNA encoding algorithm(referred to as HD-code, where HD stands for high density). The novelty and contributions of this work contain three parts. First, by taking full advantage of the statistical characteristics of the original multimedia data and considering the biological constraints on the DNA bases, the proposed scheme achieves higher logical storage density and improves the flexibility and consistency in data storage. Second, by performing data conversion, the proposed scheme can effectively encode extreme images with large proportion of single color. Third, the proposed method can reconstruct high quality images and reduce synthesis costs by yielding better rate-PSNR(Peak Signal to Noise Ratio).

Ferroelectric nanoscale logic gates by mixed dislocations in SrTiO3

Conventional nanoscale logic gates involve several critical challenges, such as the appearance of leakage currents, and so new approaches to logic calculation devices have been exploited. However, although polarization switching in ferroelectrics has certain advantages in this regard, including nonvolatility, these materials are not leading candidates for logic gates because they disappear at the nanoscale and do not typically allow the two-inputs--one-output operation which is necessary for logic gates. Here, we demonstrate the possibility that ultrasmall ferroelectric nanoscale logic gates can be generated from mixed dislocations in ${\mathrm{SrTiO}}_{3}$. Phase-field simulations show that the unique strain field associated with a mixed dislocation induces a few nanometer polarization spiral, the chirality of which can be switched by electric fields that are both horizontal and vertical to the spiral. Due to this polarization structure, or, and, and not operations can be performed depending on the strength of the electric fields. These results suggest a different means of fabricating ultrathin logic gates, and could potentially lead to energy-efficient ultrahigh logic density devices.