Superconducting pulse conserving logic and Josephson-SRAM

Abstract

Superconducting digital pulse-conserving logic and Josephson static random access memory (JSRAM) memory together enable scalable circuits with energy efficiency 100× beyond leading-node CMOS. Circuit designs support high throughput and low latency when implemented in an advanced fabrication stack with high-critical-current-density Josephson junctions of 1000 μA/μm2. Pulse-conserving logic produces one single-flux-quantum output for each input and includes a three-input, three-output gate producing logical or3, majority3, and and3. Gate macros using dual-rail data encoding eliminate inversion latency and produce efficient implementations of all standard logic functions. A full adder using 70 Josephson junctions has a carry-out latency of 5 ps corresponding to an effective 12 levels of logic at 30 GHz. JSRAM memory uses single-flux-quantum signals throughout an active array to achieve throughput at the same clock rate as the logic. The unit cell has eight Josephson junctions, a signal propagation latency of 1 ps, and a footprint of 2 μm2. Projected density of JSRAM is 4 MB/cm2, and computational density of pulse-conserving logic is on par with leading node CMOS accounting for power densities and clock rates.