Logical Correctness Research Articles

Should pluralists be pluralists about pluralism?

How many correct logics are there? Monists endorse that there is one, pluralists argue for many, and nihilists claim that there are none. Reasoning about these views requires a logic. That is the meta-logic. It turns out that there are some meta-logical challenges specifically for the pluralists. I will argue that these depend on an implicitly assumed absoluteness of correct logic. Pluralists can solve the challenges by giving up on this absoluteness and instead adopt contextualism about correct logic. This contextualism is naturalistically appealing.

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

An enhanced handover authentication solution for 6LoWPAN networks

The rapidly increasing scale of the Internet Protocol version 6 (IPv6) over Low Power Wireless Personal Area Networks (6LoWPAN) and the limitation of communication range emphasized the importance of handovers. The Proxy Mobile IPv6 (PMIPv6) was designed to manage the mobility of sensing nodes with limited resources, which has specified plenty of criteria to resolve mobility issues. However, there are still some issues regarding the security of mobility. In this paper, we proposed a more secure and efficient PMIPv6-based handover scheme compared with existing solutions. It was designed to ensure an efficient and secure roaming in 6LoWPAN networks. In this work, the initial authentication on a mobile node works based on a non-interactive zero-knowledge proof. And a session key chain established between the mobile node and the mobile access gateway is generated according to the direction of the node's movement. Therefore, when one node moves to a new domain, a full authentication on the node is not necessary so that secure and seamless handovers among different domains can be realized compared with other schemes. With this protocol, the handover of mobile devices among stations will be more seamless, efficient, and secure. The logic correctness of the proposed scheme is proved by Protocol Composition Logic (PCL). Besides that, the proposal was formally verified and evaluated in terms of performance, which shows that the proposed handover scheme in 6LoWPANs could not only enhance the security functionalities but also be computationally efficient.

مِنْ بَلاغَةِ أسَالِیبِ الاحتِجَاجِ العَقلیِّ فِی الحَدِیثِ النَّبَویِّ (القِیَاسِ والتَّمثِیلِ أُنْمُوذَجًا)

يهدف هذا البحث إلى إثبات أن النبي-ﷺ- استطاع أن يصل إلى قلوب المخاطبين بالرفق واللين، وإلى عقولهم بالإقناع والمنطق القويم، من خلال تقريب الأحکام بذکر نظائرها وأسبابها، وضرب الأمثال، فأقام النبي-ﷺ- دعوته وتعليمه على الإقناع العقلي، مستخدما لذلک أساليب متعددة، تنسجم مع أصناف المدعوين وواقعهم وأفهامهم، ومن تلک الأساليب: القياس والتمثيل، باعتبارهما من خاصة العقل؛ لأجل ذلک فقد عمدت إلى اختيار هذين الأسلوبين لتسليط الضوء عليهما، وإظهار بلاغتهما في کلام النبي-ﷺ-؛ لما لهما من دور عظيم، وأهمية بالغة، تؤدي في النهاية إلى الاقتناع، وتقرير المعاني، وتمکينها في النفوس. وقد اتبعت في هذا البحث منهج الاصطفاء في جمع الأحاديث ، ومنهج التحليل الکلي في المعالجة؛ من خلال تحليل الأحاديث- محل الدراسة- تحليلا بلاغيا، مبرزة خصائص ترکيبها، وبيان صورها، وسمات ألفاظها. ومن نتائج هذا البحث: أن القياس والتمثيل من أساليب الاحتجاج العقلي غير المباشرة في الوصول إلى المراد، ويهدفان إلى الإقناع، وإلى بيان الحقيقة، وتعديل السلوک، وتغيير المفاهيم، وترسيخ القيم الإيمانية. رفق النبي-ﷺ- بالمتلقين، ورحمته وتلطفه في الخطاب معهم، رغم امتلاکه السلطة التشريعية في حملهم على الإذعان بالأساليب الطلبية المباشرة، إلا أنه اعتمد القياس والتمثيل أسلوبا إقناعيا؛ لتقبل النفس البشرية له، مما يحملهم على سرعة الامتثال والانقياد. This research aims to prove that the Prophet (PBUH) was able to reach the hearts of the addressees with kindness and leniency, and to their minds with persuasion and correct logic, by approximating the rulings by mentioning their counterparts and their causes, and multiplying the intellect using the methods of the Prophet. The invited guests, their reality and their understanding, and among those methods: analogy and representation, as they are characteristic of the mind; For this reason, I chose these two methods to shed light on them, and to show their eloquence in the words of the Prophet because of their great role and great importance, which ultimately leads to conviction, determination of meanings, and empowerment of souls. I have followed in this research the method of selection in collecting hadiths, and the method of total analysis in treatment; Through the analysis of the hadiths - the subject of the study - a rhetorical analysis, highlighting the characteristics of their structure, their images, and the features of their words. Among the results of this research: that analogy and representation are among the indirect methods of mental protest in reaching the goal, and they aim at persuasion, clarifying the truth, modifying behavior, changing concepts, and consolidating faith values. The Prophet’s kindness to the recipients, his mercy and kindness in addressing them, despite having the legislative power to force them to submit to direct ordering methods, yet he adopted analogy and representation as a persuasive method; To accept the human soul to him, which leads them to the speed of compliance and submission.

A Model with Iterative Trials for Correcting Logic Errors in Source Code

It is difficult for students and teachers to detect and correct logic errors in source code. Compilers and integrated development environments (IDEs) have the ability to detect and correct syntax errors but it is also difficult for them to detect and correct logic errors. Although many machine learning approaches have been proposed that can show correction candidates for logic errors, they do not provide guidance concerning how the user should fix them. In this paper, we propose a model for correcting logic errors in a given source code. The proposed model realizes debugging of multiple logic errors in the source code by iterative trials of identifying the errors, correcting the errors, and testing the source code. In this model, in the first stage, a list of correction candidates is provided by a deep learning model, and then the list is given to an editing operation predictor that predicts the editing operation for the correction candidate. To learn the internal parameters of the proposed model, we use a set of solution codes created to solve the corresponding programming tasks in a real e-learning system. To verify the usefulness of the proposed model, we apply it to 32 programming tasks. Experimental results show that the correction accuracy is, on average, 58.64% higher than that of the conventional model without iterative trials.

Intelligent Internet of Things Technology in Agricultural Environment Monitoring

The application of the Internet of Things to precision agriculture is conducive to the intelligent and controllable aspects of agricultural production and management, is conducive to the implementation of green agricultural production methods, is conducive to the sustainable development of agriculture, and promotes the structural reform of the agricultural supply side. An intelligent greenhouse environment monitoring system is designed based on the Internet of Things technology, and a wireless network is established using the JenNet protocol to realize real-time monitoring of environmental factors such as air temperature and humidity, soil temperature and humidity, light intensity, and CO2 concentration in the greenhouse. Finally, the paper uses the time automata modelling tool UPPAAL to verify the system logic correctness and system execution timing verification on the established formal model. The results verify that the agricultural temperature control environment system network based on the intelligent Internet of Things operates stably, with high acquisition accuracy, low node power consumption, accurate feedback control, and meets the intelligent demand for greenhouse data acquisition and control.

Reasons, basing, and the normative collapse of logical pluralism

Logical pluralism is the view that there is more than one correct logic. A key objection to logical pluralism is that it collapses into monism. The core of the Collapse Objection is that only the pluralist’s strongest logic does any genuine normative work; since a logic must do genuine normative work, this means that the pluralist is really a monist, who is committed to her strongest logic being the one true logic. This paper considers a neglected question in the collapse debate: what is it for a logic to do genuine normative work? As well as having wider upshot for the connection between logic and normativity, grappling with this question provides a new response to the Collapse Objection on behalf of the pluralist. I suggest that we should allow logics to generate pro tanto reasons in a way that bears not just on combinations of attitudes but on how an agent’s attitudes are based on one another. This motivates adopting normative principles that allow the pluralist’s weaker logics to earn their normative keep. Rather than being ad hoc, these principles capture a sense in which good reasoning goes beyond the consistency of an agent’s attitudes. Good reasoning is also concerned with how an agent’s attitudes are based on one another.

Cascaded semiconductor optical amplifiers-based all-optical OR logic gate

We present a novel study of the ultrafast performance of an all-optical OR logic gate using two-cascaded semiconductor optical amplifiers (SOAs) at a data rate of 80 Gb s−1. The variation of the gate’s quality factor (Q-factor) against various key operating parameters, such as the continuous wave input power and wavelength, the operating data rate and the equivalent pseudorandom binary sequence length, is examined and assessed, taking into account the effects of SOAs amplified spontaneous emission and operating temperature to obtain results that are closer to reality. The simulation results indicate that the OR logic gate can be realized using the proposed two-cascaded SOAs scheme at 80 Gb s−1 with logical correctness and a Q-factor = 23.7, which is higher than that previously reported with other SOA-based schemes.

High-Performance Current-Mode Logic Ternary D Flip-Flop Based on Bipolar Complementary Metal Oxide Semiconductor

In this paper, a simple-structured and high-performance current-mode logic (CML) ternary D flip-flop based on BiCMOS is proposed. It combines both advantages of BiCMOS and CML circuits, which is with much more high-speed, strong-drive and anti-interference abilities. Utilizing TSMC 180 nm process, results of simulations carried out by HSPICE illustrate the proposed circuit not only has correct logic function, but also gains improvements of 95.6~98.4% in average D-Q delay and 16.2%~70.4 in PDP compared with advanced ternary D flip-flop. When compared at the same information transmission speed, proposed circuit is more competitive. Furthermore, it can perform up to high frequency of 15 GHz and drive heavier load. All the results prove that proposed circuit is high-performance and very suitable for high-speed and high-frequency applications.

Logos, logic and maximal infinity

AbstractRecent developments in the philosophy of logic suggest that the correct foundational logic is like God in that both are maximally infinite and only partially graspable by finite beings. This opens the door to a new argument for the existence of God, exploiting the link between God and logic through the intermediary of the Logos. This article explores the argument from the nature of God to the nature of logic, and sketches the converse argument from the nature of logic to the existence of God.

Automated Comparative Study of Some Generalized Rough Approximations

The paper contains some remarks on building automated counterpart of a comparison of some generalized rough approximations of sets, where the classical indiscernibility relation is generalized to arbitrary binary relation. Our focus was on translating rationality postulates for such operators by means of the Mizar system – the software and the database which allows for expressing and checking mathematical knowledge for the logical correctness. The main objective was the formal (and machine-checked) proof of Theorem 4.1 from A. Gomolińska’s paper “A Comparative Study of Some Generalized Rough Approximations”, hence the present title. We provide also the discussion on how to make the presentation more efficient to reuse the reasoning techniques of the Mizar verifier.

Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology

<p indent=0mm>With continuous scaling of CMOS technology, single event multi-node upset induced by charge sharing effect has become an important factor affecting chip reliability. This paper proposed a novel multi-node upset (MNU) tolerant latch design: LPMNUHL. Based on DICE latch, where single node upset is resilient, the latch builds a mechanism of triple modular redundancy and uses a voter as output. The proposed latch is tolerant to multi-node upset and votes the correct output logic value. What’s more, there is no high impedance state in the latch and soft errors of the internal nodes can be blocked successfully. The latch can not only tolerance triple node upset completely, but also tolerance 90.30% of quadruple node upset. Due to the use of a high-speed transmission path, the clock-gating technology and a clock-gating voter, the proposed latch is low power. In <sc>32 nm</sc> CMOS technology, extensive SPICE simulation results demonstrate that compared with the previous latches, the proposed latch has an average delay reduction of 40.16%, an average power reduction of 44.96%, an average power delay product reduction of 65.40%, and an area reduction of 34.60%. Moreover, the proposed latch is not sensitive to temperature and voltage variations.

Construction of the Definition of the “Credit” Category

The subject of the research is the essence, nature and meaning of the “credit” category. The goal is to develop a definition of the “credit” category reflecting the nature of the phenomenon it refers to. Hypothesis: the author believes that general scientific research methods based on the idea of triadicity will reveal and describe the nature of the phenomenon of credit, as well as formulate a scientifically based definition of the corresponding category. Methods: formal-logical method, method of triadic decoding of categories. As a result of using the formallogical method the author defined: a) the generic concept “loan” as a universe, part of which is the “credit” category; b) non-credit forms of loans: “bill”, “bond”, “factoring”, “leasing”; c) necessary and sufficient conditions for classifying an object as a “credit”. A scientifically grounded definition of the “credit” category was formulated. As a result of deciphering the “credit” category, the essential qualities in the “credit” object, which together make up its essence, nature and meaning, were revealed; a detailed definition of the “credit” category was received. The research into the nature of credit has shown that the closest generic concept of credit is a loan; a necessary condition for classifying a credit as a loan is the transfer or receipt of money and goods on loan; repayment, payment and urgency are sufficient conditions for classifying a credit as a loan category; as a result, “credit” is defined as a kind of loan categories, the objective essential properties of which are repayment, payment and urgency. The field of applicability of the results in theory: the possibility of using the formal-logical method to investigate the nature of the research object; to check the obtained definition of the object for logical correctness; to enter your own definitions of the research object into the subject field with the help of “triads”. In lending practice the results are applicable as follows: scientifically grounded definition of the “credit” category, understanding the essence and nature of credit, its properties: repayment, payment and urgency to determine the specific variety of credit.

Pattern Recognition: Theoretical Research Experience and Applications

The article offers a brief overview of the main theoretical and practical results obtained by its authors and their scientific followers. The results concern mainly the deterministic theory of pattern recognition. In particular, the main results on the logical and algebraic correction of heuristic algorithms are presented. Possible directions for the development of recognition algorithms based on inductive inference, similarity, and precedence metrics are also proposed. The practical part deals with some of the decision-making tasks in areas such as medical diagnostics and various technical areas. The nature of the review and value judgments is based on the experience of the authors.

Is English consequence compact?

By mimicking the standard definition for a formal language, we define what it is for a natural language to be compact. We set out a valid English argument none of whose finite subarguments is valid. We consider one by one objections to the argument's logical validity and then dismiss them. The conclusion is that English—and any other language with the capacity to express the argument—is not compact. This rules out a large class of logics as the correct foundational one, for example any sound and complete logic, and in particular first-order logic. The correct foundational logic is not compact.

On the Controversy over the Logical Correctness of Einstein’s First Paper on Mass-Energy Equivalence

It is well-known that Einstein’s first attempt to explain E = mc2 which was published in Annalen der Physik in 1905, has been criticized as problematic. In particular, it has been shown by Ives and reiterated by Jammer that it suffers from the error of circular reasoning. Attempts have been made in the scientific literature to discount the circular reasoning objection of Ives, Jammer, Arzeliès and others. Fritz Rohrlich in 1990 gave a remarkably simple and concise derivation of E = mc2 along lines similar to Einstein’s but based on both momentum and energy conservation, in contrast to Einstein’s which uses only energy considerations. Rohrlich’s approach using momentum conservation is an alternative to Einstein’s, which is free from objection in logical error, and we make it quite clear on the importance of the implicit assumption of momentum conservation in any attempt to refute the circular reasoning error in Einstein’s paper. It is our contention that this point is overlooked or altogether avoided by those who have attempted to uproot the circular reasoning criticism of Einstein’s paper.

Digital Error Correction Logic for Pipelined ADC Using 1.5Bits/Stage

Low power, high resolution and high-speed ADCs are becoming increasingly important with advancements in portable electronics, from mobile phones and pagers to CD players and MP3 players. This is certainly not feasible on a handheld device which is why new ADC techniques must be developed. They are becoming increasingly attractive to major data converter manufacturers and their designers because pipeline ADCs provide an optimal balance of scale, speed, resolution, power dissipation and analogue design effort. Because of latency and errors in comparators & gain stages in pipelined ADCs, the need arises for digital error correction mechanism. The digital error correction logic will be implemented for 8-bit ADC using 1.5 bits per stage. While designing we are considering important parameters of CMOS like propagation delay performance and power dissipation. The VLSI realization of digital arithmetic is implemented using TANNER EDA software tool using 0.18µm CMOS process.

Noise-free logic and Set-Reset latch operation in a triple-well potential system

We demonstrate additive driving force can induce logic and Set-Reset latch operation in a triple-well potential system and find the optimal parameter region with contour maps. The logic input signal plays the role of system bias. To be specific, the external driving force makes the system jump from high potential well to low potential well without jumping back, and thus can induce correct logic output. The problem that the optimal parameter region is too narrow can be solved in two ways: one is to increase the amplitude of the logic input signal, and the other is to introduce of logical vibration resonance. In addition, the logic input itself can be directly acted as the driving force to make the system in the correct potential well, that is, to achieve the correct logic and Set-Reset latch operation without other external driving force.

A lightweight authentication and key exchange mechanism for IPv6 over low‐power wireless personal area networks‐based Internet of things

AbstractThe authentication mechanism in IPv6 over low‐power wireless personal area networks (6LoWPAN) uses media access control identifier and IPv6 address. The traditional wireless sensor network considers three‐factor authentication mechanism. These factors, namely, username, password, and biometric create a huge overhead in Internet of things due to resource‐constraint devices in terms of low memory and processing capabilities. In this article, we propose a lightweight key exchange and authentication scheme for 6LoWPAN to efficiently authenticate the resource‐constraint sensor devices. The proposed scheme uses hash‐based approaches in the setup and registration phase to reduce the computational cost and resource consumption overhead. The analytical results over the automated validation of internet security protocols and applications and ProVerif tools validate the security claim of the proposed scheme against threats like replay and man‐in‐the‐middle attack. Furthermore, we analyze the logic correctness of the proposed authentication scheme using Burrows‐Abadi‐Needham logic.

Defective cell reuse based defect-tolerance method for CMOL cell mapping optimization

Due to the high defect rate of nanodevices and nanowires in the process of manufacturing, the defect-tolerance mapping in CMOS/nanowire/molecule hybrid (CMOL) circuit is a key step to achieve the correct logic function. However, a high defect rate may reduce the success rate of defect-tolerance mapping because of the shortage of mapping resources. In this paper, a defective cell reuse based defect-tolerance mapping optimization method is proposed to address the mapping problem under limited mapping resources in defective CMOL circuits. First, stuck-at-close defect is analyzed and the constraint of reusing defective cells is proposed. Second, the logic hierarchy based mapping framework is undertaken to improve the mapping success rate and the performance of mapped CMOL circuit. Finally, the method is embedded into Tabu Search (TS) algorithm to verify the feasibility and efficiency. Experimental evaluation on ISCAS benchmark shows that compared with the existing methods, the proposed method has a higher defect-tolerance mapping success rate and a better mapped performance.