Defective cell reuse based defect-tolerance method for CMOL cell mapping optimization

Abstract

Due to the high defect rate of nanodevices and nanowires in the process of manufacturing, the defect-tolerance mapping in CMOS/nanowire/molecule hybrid (CMOL) circuit is a key step to achieve the correct logic function. However, a high defect rate may reduce the success rate of defect-tolerance mapping because of the shortage of mapping resources. In this paper, a defective cell reuse based defect-tolerance mapping optimization method is proposed to address the mapping problem under limited mapping resources in defective CMOL circuits. First, stuck-at-close defect is analyzed and the constraint of reusing defective cells is proposed. Second, the logic hierarchy based mapping framework is undertaken to improve the mapping success rate and the performance of mapped CMOL circuit. Finally, the method is embedded into Tabu Search (TS) algorithm to verify the feasibility and efficiency. Experimental evaluation on ISCAS benchmark shows that compared with the existing methods, the proposed method has a higher defect-tolerance mapping success rate and a better mapped performance.