Logic Utilization Research Articles

An Energy Efficient VLSI Architecture of Decision Feedback Equalizer for 5G Communication System

Decision feedback equalizer (DFE) is widely used to mitigate the inter-symbol interference. In gigabit applications, the complexity of time domain DFE grows exponentially with feedback filter (FBF) order. In this paper, we have derived low complexity, high throughput architectural designs for time domain DFEs, which meets the requirements of 5G communication systems. These designs are based on the concept of pre-speedup the conventional DFE architecture. The number of FBF coefficient combinations to be stored in the lookup table (LUT) and the hardware complexity of proposed designs are reduced by almost $(M/2)^{-1}$ with $M$ being the number of levels in quadrature-amplitude modulation (QAM). The proposed design achieves the throughput nearly 2.15 Gb/s for 16-QAM. A new strategy for updating the FBF coefficients is proposed to improve the convergence rate and steady state error performances without extra hardware overhead. This is based on storing the past decisions in separate LUT, whose contents are updated time to time using parallel error multiplexor. In addition, the bit-error-rate performance of proposed designs is evaluated for different speedup factors in AWGN and Rayleigh fading channels. From the implementation results, it is found that the area, power, and logic utilization of the proposed designs are significantly reduced. For example, an $8^{\mathrm{ th}}$ -order FBF of proposed adaptive DFE for 16-QAM occupies times 1.19 less area, 1.04 times less area-time product, with nearly consumes 2.48 times less power and; utilizes 1.93 times less slice LUTs and 2.04 times less flip-flops as compared with the best existing scheme.

Understanding the nittygrities of software reliability and its testing procedures: A different approach

The development of software is a complicated task and involves a lot of deliberate elaboration on part of user as well as developer. The user must spell out the requirements in detail and feed all the required inputs to the developer to analyse the environmental conditions, HR restrictions, Exploitation and utility aspects of the software being asked for. For its reliability testing, the developer may choose the method and tools of his choice. It is required that due consideration be given to large number of factors to decide onto the reliability testing technique. These include calculating and documenting factors like ROCOF, MTTF, MTTR, MTBF, POFOD, Probability and Availability. The Software Reliability checking is an essential aspect which demands due deliberation and there are various Software Reliability Models that are in place worldwide. Software Reliability Modelling started initially with OOPS and later graduated to Component Based Software System (CBSS) for the sake of reusability and simplicity. Fuzzy logic being one of the CBSS approach, is discussed in detail. Fuzzy logic refers to the concept which is completely opposite of Boolean Logic of ‘0’ and ‘1’. Fuzzy logic suggests that there are infinite number of possibilities between ‘0’ and ‘1’. In this paper, the utility of Fuzzy logic for ensuring the safety and security aspects of various social networking sites has also been discussed in detail giving various examples.

Performance Evaluation of Verilog Coding Techniques for Optimized MD5 Algorithm

Nowadays all electronic devices focus on high performance implementation. One of the well-known methods to represent the concept of hardware implementation is HDL design style, where Verilog HDL and VHDL are widely used as Hardware Description Language (HDL). These HDLs are portable and technology-independent. Verilog HDL code focuses on bottom-up system design while VHDL focuses on top-down design. Efficient coding can cause better performance but bad coding may degrade performance even if the system is successfully designed. This paper discusses the performance analysis of MD5 design in term of frequency maximum, logic utilization and power analysis for both MD5 design with and without controller. FPGAs provide flexibility for their re-configurability and low cost. Therefore, FPGAs are suitable to implement various design implementation caused by different coding styles. In this paper, MD5 algorithms are designed using Verilog, then synthesized and simulated using Altera Quartus II and ModelSim. The maximum frequency of MD5 design improve significantly with 135.78 MHz. The total register is 586 and combinational ALUT is 712. Besides, the power of the MD5 design is analyzed by filtering the glitch in the power analysis section. Thus, Verilog HDL Coding Style and Altera Quartus II play an important role in designing high-performance design.

PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era

Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of Reconfigurable Hard Logics (RHLs) and a small-input LUT. In the proposed architecture, we selectively turn off unused RHLs and/or LUTs within each logic block by employing a reconfigurable controller. By mapping a majority of logic functions to simple-design RHLs, PEAF is able to significantly improve power efficiency without deteriorating the performance. Experimental results over a comprehensive set of benchmarks (MCNC, IWLS'05, and VTR) demonstrate that compared with baseline four-LUT architecture, PEAF reduces the total static power and Power-Delay-Product (PDP), on average, by 24.5 and 21.7 percent, respectively. This is while the overall system performance is also improved by 1.8 percent. PEAF increases total area by 18.9 percent, however, it still occupies 22.1 percent less area footprint than the six-LUT architecture with 31.5 percent improvement in PDP.

Design and efficient hardware implementation schemes for non-Quasi-Cyclic LDPC codes

The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic (NQC) Low-Density Parity-Check (LDPC) codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing (MOMP) algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing (OMP) technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-dB coding gain for Binary PhaseShift Keying (BPSK) in an Additive White Gaussian Noise (AWGN) channel, the decoder with the proposed scheme achieves a 23.8%-52.6% reduction in logic utilization per Mbps and a 29.0%-90.0% reduction in message-memory bits per Mbps.

Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm

Somewhat Homomorphic Encryption (SHE) schemes allow to carry out operations on data in the cipher domain. In a cloud computing scenario, personal information can be processed secretly, inferring a high level of confidentiality. For many years, practical parameters of SHE schemes were overestimated, leading to only consider the FFT algorithm to accelerate SHE in hardware. Nevertheless, recent work demonstrates that parameters can be lowered without compromising the security [1] . Following this trend, this work investigates the benefits of using Karatsuba algorithm instead of FFT for the Fan-Vercauteren (FV) Homomorphic Encryption scheme. The proposed accelerator relies on an hardware/software co-design approach, and is designed to perform fast arithmetic operations on degree 2,560 polynomials with 135 bits coefficients, allowing to compute small algorithms homomorphically. Compared to a functionally equivalent design using FFT, our accelerator performs an homomorphic multiplication in 11.9 ms instead of 15.46 ms, and halves the size of logic utilization and registers on the FPGA.

A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

Real-time multimedia data access plays an important role in electronic systems; as time goes by, with decrease in data processing speed and increase in communication time, storage time, and retrieval time, the overall response time increases for real-time applications. Therefore, in this paper, a novel real-time, fast, low-cost, system-on-chip (SoC) controller has been proposed and implemented where large volume of data can be efficiently stored and retrieved from flash memory cards. It is being implemented only using hardware description language (HDL) on a field programmable gate array (FPGA) chip without using any other on-board or external hardware resources or high-level languages. The entire controller architecture, in a single chip, contains five different modules and is designed using finite state machine (FSM)-based approach. The modules are card initialization module (CINM), idle module (IM), card read module (CRM), card write module (CWM), and decision module (DM). The architecture is completely synthesized for Spartan 3E xc3s500e-4-fg320 FPGA with only 5% of the total logic utilization. The experimental results tested for microSD, SD, and SDHC cards of different size, and these show that the architecture uses less hardware and clock cycles for card initialization and single/multiblock read/write procedure.

Simple utilization of lactic acid whey in dairy processing

Abstract The use of ultra-filtered lactic acid whey retentate was investigated for the making of sour cream. The utilization of lactic acid whey is limited due to its special properties, so the logical utilization way is to use it in fermented products. First, we concentrated lactic acid whey collected from cottage cheese making by ultrafiltration (UF), then UF Whey Retentate (UFWR) was added (by 2, 5, and 10%) into fat standardized cream for sour cream making. We investigated the texture and sensory properties of the sour cream samples compared with the industrial products. Generally, we can state that the use of small portion of UF whey retentate did not result noticeable changes and did not reduce the sensory value of sour creams. Higher UF whey retentate addition improved some texture properties of experimental samples, but the summarized evaluation of UFWR addition was not unequivocal. Control samples showed better results. Based on our results, the sample, which contained 5% UF whey retentate, had good texture and acceptable sensory properties. Furthermore, more than 5% UF lactic acid whey retentate (coming from our own ultrafiltration process) resulted remarkably worse sensory properties than the other samples. Further investigation is needed to find the optimal composition and sensory properties of UFWR. Furthermore, we have to perform technological investigation to reach a higher concentration factor using pre-treatment of whey and to avoid the precipitation of whey proteins during the high temperature pasteurization of cream, cream mixed with UFWR or diafiltered whey retentate. We guess that the use of one-stage diafiltration would already decrease the unfavourable sensory properties of lactic acid whey retentate.

FPGA Implementation Issues of a Flexible Synchronizer Suitable for NC-OFDM-Based Cognitive Radios

This paper presents a flexible timing synchronization scheme alongside the hardware implementation issues on an Altera Stratix-V Field Programmable Gate Array (FPGA) device. The core content of the synchronizer is based on Finite Impulse Response (FIR) filter which operates as a multicorrelator on demand. The term flexibility refers to a specific part of the synchronizer where the multicorrelator reconfigures its FIR filter block on-the-fly by employing Partial Reconfiguration (PR) feature. Moreover, different implementations have been evaluated for the multicorrelator, including MultiplierLess (ML) approach (an approximate computing technique only for autocorrelation purpose) along with the Direct From as well as the Transposed, Parallel, and Pipelined-Parallel Direct Form FIR filters. All the developed architectures are compared to each other in terms of power consumption, silicon area, and maximum frequency. Preliminary synthesis results show that the ML approach achieves better performance (including 94% less power dissipation, 75% less logic utilization as well as 67% fewer registers) than other architectures when performing autocorrelation function. Furthermore, the critical path is analyzed and appropriate optimization techniques (such as DSP register packing and intermediate register insertion) are applied to the best candidates of the architectures mentioned. As the best results, 2.83 speed-up, 56.57% less logic utilization along with 38.86% fewer registers are achieved for different architectures. Accordingly, we discover that the parallel form, as well as the pipelined-parallel one, achieve more interesting results than the transposed version in most of the cases.

Likud’s success in the 2015 elections: Netanyahu’s Hobbesian moment

The current article develops an explanation for Likud’s success, which goes beyond the existing structural and circumstantial accounts. It argues that Likud’s success should be sought for in the utilization of Hobbesian logic by its leader, Benjamin Netanyahu. By revealing the commonalities between Hobbes’s political thinking and Rhetoric, and Netanyahu’s political conduct, this paper sheds new light on Netanyahu’s leadership and sources of legitimation and authority in Israel, which are understudied. We demonstrate that Netanyahu’s Hobbesian dimension is best reflected in his understanding of the nature of civil and political rights in the context of an ongoing struggle for survival and self-determination.

High-Resolution Synthesizable Digitally-Controlled Delay Lines

Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation.

Fast Motion Estimation Based on Perceptual-Aware for the Depth Map Coding in 3DVC

This paper proposes a perceptual-aware mode decision algorithm to reduce the coding time of 3D video coding (3DVC) with 2D plus depth maps. The algorithm utilizes a factor called ＂interesting activity＂ to determine the interesting region and its candidate coding modes of the depth map. The interesting activity is defined based on the characteristic of visual perception for 3D video viewers, where the characteristics are presented by the existence of MBs with object feature in foreground, or with motion information. In interesting regions, the quality of constructed depth map is maintained; in the non-interesting regions, the computation time of the depth map coding is reduced. In the final step of the algorithm, we use the third dimensional search to improve the quality of the re-constructed depth map. Furthermore, the proposed algorithm is implemented in FPGA to achieve a hardware design. Experimental results show that the entire encoding time is reduced by at least 50.6% compared with the exhaustive mode decision approach, and the structural similarity (SSIM) index is increased by at least 0.0291 and the Peak Signal to Noise Ratio (PSNR) is increased by at least 4.67dB compared with the motion vector (MV) sharing approach. The logic utilization only occupies 8% of the total resource on the Altera DE3-260 FPGA demonstration board.

ASIC Design of Natural Frequency of ECG Signal for Atrial Fibrillation Detection Module using High-Level Synthesis Approach

The growth of interest in the development of reduced-scale electrocardiogram (ECG) system based on field-programmable gated-array (FPGA) design platform is increasing. This study provides initial result of mapping digital signal processing to hardware design for specific purpose. In this paper, a part of digital signal processing for atrial fibrillation classification was implemented to register-transfer level (RTL) design. The specific part was feature extraction of ECG signal. The algorithm of ECG signal feature extraction was natural frequency from second-order system for detecting atrial fibrillation. By applying high-level synthesis method, three designs were implemented for natural frequency behavior. The designs were two Single-Cycle (Design 1 and Design 2) and Multi-Cycle fully-constraint (Design 3), of which logic utilization consist of 2530, 36 and 1, respectively. Performance evaluation among all designs were compared.

English

Malaria presents a diagnostic challenge in most tropical countries. Rapid detection of the malaria parasite and early treatment of infection still remain the most important goals of disease management. Therefore, performance characteristics of the indigenous RDTs was determined among children with suspected malaria fever attending pediatrics OPD or admitted in indoor of UP RIMS n R Saifai central India, to assess whether this rapid diagnostic test (RDT) could be used for diagnosis of malaria and results were compared with Gold Standard microscopy test. We also assessed the logical utilization of RDTs to monitor treatment outcome. MATERIALS AND METHODS: 03 months to 12 years old children who were presented with acute fever without any focus to the OPD or IPD of our department from May 2011 to April 2013 were selected for the study. A finger prick blood sample was collected from each clinically suspected case of malaria to prepare blood smear and for testing with the RDT after taking informed consent. The blood smears were read by an experienced microscopist blinded to the RDT results and clinical status of the subjects. The figures for specificity, sensitivity, accuracy and predictive values were calculated using microscopy as gold standard. RESULTS: Analysis revealed that overall sensitivity, specificity and accuracy of the RDT were approx. 90%, while RDT is useful to confirm the diagnosis of new symptomatic cases of suspected malaria infection, the persistence of parasite antigen leading to false positives even after clearance of asexual Parasitaemia has limited its utility as a prognostic tool. The study showed that RDTs was easy to use, reliable and cheap for diagnosing new malaria cases, and is an appropriate test for the use in the fields and remote areas.

Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function

This paper presents the hardware implementation of an evolvable block-based neural network that utilizes a novel and cost efficient sigmoid-like activation function. Evolvable block-based neural networks (BbNNs) feature simultaneous optimization of structure, and viable implementation in reconfigurable digital hardware such as field programmable gate arrays (FPGAs). Efficient hardware implementation of BbNN structures is the primary goal of this paper. Various aspects of BbNN modeling and design considerations are presented. The neuron blocks are designed with properly described methodology, using only a single multiplier each, and implement a cost efficient sigmoid-like activation function. A novel method of reusing the multiplier to smoothly approximate a hyperbolic tangent (tanh) function to be used as the activation function for the neuron blocks is also presented. This is an important contribution, because a sigmoid-like activation function is provided at almost no additional cost. The neuron blocks are very cost efficient in terms of logic utilization when compared to the previous work. The BbNN is designed as an system-on-chip (SoC), and is functionally verified and tested on several case studies. The system performance allows real-time classification, and executes up to 410×faster than embedded software.

VLSI architecture for LGXP texture for face recognition

VLSI architecture for face recognition system based on Local Gabor XOR Pattern (LGXP) feature extraction method is presented in this paper. LGXP is utilized to encode Gabor phase variations and to extract feature with the help of Gabor filter and Local XOR Pattern (LXP) operator. VLSI architecture for Gabor Filter and a Behavioral model for LXP operator for feature extraction are investigated. Also a behavioral model for Similarity matching is designed using Verilog language. The similarity matching for face recognition is executed by L1 distance measure. Therefore our approach explores the effectiveness of Gabor phase information on FPGA platform by addressing the drawbacks like computational complexity and hardware complexity by mapping the algorithms. The proposed approach is designed on virtex-5 device using Veriolg HDL in Xilinx ISE tool and the logic utilization results will be generated using synthesis tool while the power consumption report will be analyzed using Xpower analysis tool. Also the effectiveness of our design is evaluated with FAR, FRR and accuracy plot in Matlab simulation environment. Research outcome of our proposed face recognition system over UPC face database is 72.225% Accuracy for distance matching threshold of '5'.

Generalized Hardware Post-processing Technique for Chaos-Based Pseudorandom Number Generators

This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations.

IMPROVED TIME-MULTIPLEXED FPGA ARCHITECTURE AND ALGORITHM FOR MINIMIZING COMMUNICATION COST DESIGNS

The Time-Multiplexed FPGA (TMFPGA) architecture can improve dramatically logic utilization by time-sharing logic but it needs a large amount of registers among sub-circuits for partitioning the given sequential circuits. In this paper, we propose an improved TMFPGA architecture to simplify the precedence constraints so that the number of the registers among sub-circuits can be reduced for sequential circuits partitioning. To demonstrate the practicability of the architecture, we also present a greedy algorithm to minimize the maximum number of the registers. Experimental results demonstrate the effectives of the algorithm.

Optimization of Processor Architecture for Sobel Real-Time Edge Detection Using FPGA

This paper presents an optimized processor architecture for Sobel edge detection operator on field programmable gate arrays (FPGA). The processor is optimized by the use of several optimization techniques that aim to increase the processor throughput and reduce the processor logic utilization. FPGA offers a high level of parallelism which is exploited by the processor to implement the parallel process of edge detection in order to increase the processor throughput and enable the processor to meet real-time performance constraints. To achieve real-time performance, the proposed processor consists of several Sobel instances that are able to produce massive output pixels in parallel. This parallelism enables data reuse within the processor block which reduces the number of calculations while increasing the processor throughput. Moreover, the processor gains performance with a factor equal to the number of instances contained in the processor block. By the application of the optimization techniques, the proposed Sobel processor is able to meet real-time performance constraints due to its high throughput even with a considerably low clock frequency. In addition, the logic utilization of the proposed processor is low compared to other Sobel processors when implemented on ALTERA Cyclone II DE2-70 board

HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems

This paper describes the implementation of a reconfigurable hardware-based genetic algorithm (HGA) accelerator using the hardware-software (HW/SW) co-design methodology. This HGA is coupled with a unique TRNG that extracts random jitters from a phase lock loop (PLL) to ensure proper GA operation. It is then applied and benchmarked with several case studies, which include the optimization of a simple fitness function, a constrained Michalewicz function, and the tuning of parameters in finger-vein biometrics. A HGA solution is necessary in systems that demand high performance during the optimization process. However, implementations that are completely designed in hardware will result in a very rigid architecture, making it difficult to reconfigure the system for use in different applications. This paper aims to solve this issue by proposing a HGA design that provides reconfigurability and flexibility by moving problem-dependent processes into software. The prototyping platform used is an Altera Stratix II EP2S60 FPGA prototyping board with a clock frequency of 50 MHz. The HW/SW co-design technique is applied, and system partitioning is done based on aspects such as system constraints, operational intensity, process sequencing, hardware logic utilization, and reconfigurability. Experimental results show that the proposed HGA outperforms equivalent software implementations compiled with an open-sourced C++ GA component library (GAlib) running on the same prototyping platform by 102 times at most. In the final case study, the application of the proposed HGA in tunable parameter optimization in finger-vein biometrics improved the matching rate, reducing the equal error rate (EER) value from 1.004% down to 0.101%.