Logic Operations Research Articles

ALGORITHMIC DIFFERENCES OF COMPLETE AND PARTIAL ALGEBRAIC SYNTHESIS OF A FINITE STATE MACHINE WITH DATAPATH OF TRANSITIONS

Context. The problem of algorithmization the search for formal solutions of the problem of algebraic synthesis of a finite state ma-chine with datapath of transitions is considered. The concept of complete and partial solutions of this problem is proposed. The object of research is the automated synthesis of the finite state machine in the part of the function of transitions without taking into account the function of outputs. The basis of the algebraic implementation of the transition function is the author's approach to the transformation of state codes using a set of arithmetic and logical operations. The search for formal solutions to the problem of algebraic synthesis is a complex process that requires the use of appropriate methods and algorithms aimed at special coding of states and mapping of operations of transitions to individual state machine transitions. The use of partial solutions of the problem of algebraic synthesis can contribute to reducing the executing time of such algorithms and reducing the overall design time of digital control devices based on a finite state machine with an datapath of transitions. Objective. Development and research of algorithms for finding complete and partial solutions to the problem of algebraic synthesis of a finite state machine with datapath of transitions. Method. The research is based on the structure of a finite state machine with datapath of transitions. The synthesis of the circuit of the state machine involves the preliminary solution of the problem of algebraic synthesis. The result is the so-called formal solution of this problem, which contains two components. The first component is defined state codes, the second component is arithmetic and logic operations mapped to separate state machine transitions. Finite state machine can be synthesized in that case if transformation of given state codes in the process of making transitions is possible using a given set of operations. Verification of this possibility is carried out using the known matrix approach. It involves the formation and element-by-element mapping of two matrices – the matrix of transitions and the combined matrix of operations. As a result, a coverage matrix is formed, which reflects the possibility of implementing (covering) of state machine transitions by specified arithmetic and logic operations. Changing the way of encoding states or the set of operations can give different solutions to the problem of algebraic synthesis with a greater or lesser number of covered state machine transitions. Results. Using the example of an abstract graph-scheme of the control algorithm, it is demonstrated that the solution of the problem of algebraic synthesis of a finite state machine with datapath of transitions can be considered a situation when one or more state machine transitions cannot be implemented using a given set of operations. It is proposed to call such situation as a partial solution of the problem of algebraic synthesis. The implementation of all transitions by specified operations gives a complete solution of this problem, but the number of complete solutions is always much smaller than the number of partial solutions. Therefore, in the general case, the search for complete solutions takes much more time and, moreover, is not always possible. Conclusions. The design of a logical circuit of a finite state machine with datapath of transitions is possible in the case of a complete or partial solution of the problem of algebraic synthesis. In the case of a partial solution, those transitions that cannot be implemented by any of the available operations are implemented in a canonical way using a system of Boolean equations. The search for complete solutions generally takes more time than the search for partial solutions. This makes actual the development of algorithms and methods of synthesis of this class of finite state machine, based on the search for partial solutions of the problem of algebraic synthesis.

Repositories of Research Data in Russia and Abroad

One of the effective tools for providing open access to academic research results are repositories of various types. The most common are thematic, national, research and institutional repositories that usually contain text materials: monographs, scientific publications, conference proceedings, etc. In addition to the types mentioned above, thematic and universal research data repositories have been actively developed abroad in recent years. Besides text information, they also include numerical, audiovisual data, datasets, models, computer codes, etc. In order to assess the current state of data repositories in our country, we have conducted a study of websites of scientific organizations of the three categories that were approved by the Federal Agency for Scientific Organizations, in accordance with the Decree of the Government of the Russian Federation of April 8, 2009 No. 312 “On the Assessment and Monitoring of the Effectiveness of Scientific Organizations Performing Research, Development and Technological Work for Civil Purposes” as well as of educational institutions that are participants of the program “Priority 2030”. This work has identified only three educational institution’s data repositories, the content of which is mostly closed for a remote user. Among scientific institutions, information on research data was found on 20 websites. However, most of this information is presented as a list of data, without providing search options by various attributes and managing their results. In the meantime, we have found successful examples of functioning of Russian data repositories that include unique collections of scientific research and provide open access to the research results. They provide extensive search features for a remote user: possibilities of applying logical operators and faceted navigation, as well as sorting of search results. It has been found out that national data repositories are practically not covered in international aggregators, and the existing information about them is often incorrect. This has a negative impact on the visibility of research results within the global scientific community. At the same time, placing research data in repositories and making data repositories available in international aggregators promote visibility, accessibility and rapid distribution of research results. This eliminates the need for re-collection of data and prevents duplication of works.

AN APPROACH TO THE THEORETICAL FOUNDATIONS OF ELECTRONIC CIRCUIT DESIGN: SHEFFER STROKE HILBERT ALGEBRAS AND FUZZY SETS WITH THRESHOLDS

The Sheffer Stroke (also known as the NAND operator) is an important logical operator used in digital circuits based on the theory of fuzzy sets. The concept of fuzzy subalgebras (or fuzzy ideals) with thresholds in Sheffer Stroke Hilbert algebras is introduced. Several properties of these fuzzy subalgebras (fuzzy ideals) are discussed, and their generalizations are proven. Furthermore, the relationships between fuzzy subalgebras (fuzzy ideals) with thresholds and their level subsets are explored in detail.

Cryo-SIMPLY: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing.

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures.

BP-IMCA: An Energy-Efficient 8T SRAM-Based Bit-Parallel In-Memory Computing Architecture

In-Memory Computing (IMC) is an emerging paradigm that aims to shift computational workload away from CPUs. The bit-serial IMC architecture suffers from larger latency when performing logic and arithmetic operations. In this paper, a general-purpose, energy-efficient Bit Parallel IMC Architecture (BP-IMCA) based on Area-Optimized (AO-8T) static random access memory (SRAM) bit-cell is proposed to perform In-Memory Boolean Logic Computation (IMBC) and Near-Memory Arithmetic (NMA) operations with variable bit-width from 1- to 8-bit. The decoupled read/write paths of the employed AO-8T SRAM bit-cell eliminate compute disturbance during IMBC and NMA operations. A self-terminating read word line decoding scheme is proposed to disconnect the RBL discharging path from GND, which decreases the energy consumption of the proposed IMC architecture by 27.71% at 1[Formula: see text]V for IMBC operations. In addition to this, a [Formula: see text]-based Low-offset Symmetric Differential Sense Amplifier (LSDSA) is proposed to achieve fast and reliable sensing for both normal read and IMBC operations in the proposed IMC architecture. Further, a 4[Formula: see text]Kb SRAM array is implemented in 65-nm technology to analyze the IMC architecture at a supply voltage of 1[Formula: see text]V. The operating frequency of 1,355[Formula: see text]MHz and average energy consumption of 7.04[Formula: see text]fJ/bit is achieved during logic (IMBC) operations. The 8-bit addition and 8-bit multiplication operations achieve an energy efficiency of 11.1 TOPS/W and 2.28 TOPS/W, respectively, at 1[Formula: see text]V and 970[Formula: see text]MHz. Cumulatively, the proposed architecture achieves the lowest figure of merit compared to the state-of-the-art IMC architectures.

A low power design using FinFET-based 2N-N-2P adiabatic logic based 4 × 4 and 8 × 8 Reduced Complexity Wallace Tree Multiplier

ABSTRACT Multiplier circuits are essential components in the majority of arithmetic computations. In the VLSI industry, IC designers are increasingly concerned with ensuring low power consumption and high speed of components. From the various data processing processors; the Wallace Tree Multiplier (WTM) is one of the quickest multipliers for performing fast arithmetic functions. It is a powerful speed and strength multiplier. The adiabatic logic style is one method that is appealing for low-power electronics applications. The Reduced Complexity Wallace Tree Multiplier (RCWM) structure has the potential for area and power reduction. Here, present a FinFET-based 2N-N-2P adiabatic logic that uses fewer transistors and is more energy efficient than standard circuit schemes in this work. The ongoing scaling of MOSFETs to lower technology nodes has resulted in issues such as short-channel effects and increasing leakage currents. FinFETs can replace MOSFETs in this scenario because their gate structure completely encompasses the channel, a unique property that avoids the single-channel effect seen in MOSFETs. This article analyzes the effectiveness of energy recovery circuit designs using FinFETs that consume less energy. Performed a comparative analysis of the energy efficiency of FinFET-based 2N-N-2P, 2N2N2P, and Positive Feedback Adiabatic Logic (PFAL). The simulation results also validate the robustness and efficiency of the FinFET-based 2N-N-2P adiabatic logic circuit under varying process parameters in FinFET technology. The adiabatic logic removes all redundant logic operations present in the existing RCWM.

Self-defined dual charge percolation networks for solution-processed multithreshold transistors

This study demonstrates multithreshold engineering of a solution-processed heterojunction electrochemical transistor using a blend of n-type CdSe tetrapod-shaped nanocrystals (TpNCs) and an n-type polymeric organic semiconductor (OSC). The unique geometry of TpNCs enables a broad concentration range of charge percolation, where charge transfer between TpNC and OSC domains determines multiple threshold voltages. The OSC domain’s threshold voltage shifts from 1 to −1 V as TpNC content increases, while the TpNC domain maintains a threshold above 1.5 V. This allows for stable intermediate states, crucial for multivalued logic operations. Charge percolation and photoluminescence studies show selective charge redistribution, shifting the threshold voltages in the polymer networks. Ternary logic gates, including TNOT, TNAND, and TNOR, based on these heterojunction transistors, were also demonstrated, highlighting the potential of this approach for advanced logic applications.

Ternary Logic Transistors Using Multi-Stacked 2D Electron Gas Channels in Ultrathin Oxide Heterostructures.

2D electron gas field-effect transistors (2DEG-FETs), employing 2DEG formed at an interface of ultrathin (≈6nm) Al2O3/ZnO heterostructure as the active channel, exhibit outstanding drive current (≈215µA), subthreshold swing (≈132mV dec-1), and field effect mobility (≈49.6 cm2V-1 s-1) with a high on/off current ratio of ≈107. It is demonstrated that the Al2O3 upper layer in Al2O3/ZnO heterostructure acts as the source/drain resistance component during transistor operations, and the applied potential to the 2DEG channel is successfully modulated by Al2O3 thickness variations so that the threshold voltage (Vth) is effectively tuned. Remarkably, double-stacked 2DEG-FETs consisting of two Al2O3/ZnO heterostructured 2DEG channels with a single gate exhibit multiple Vth, enabling a ternary logic state in a single device. By inducing a voltage difference between the stacked channels, a sequential operation of the upper and lower FETs is achieved, successfully realizing a stable ternary logic operation.

Red tide identification in coastal regions based on the logical operation of multi-band spectral indices

ABSTRACT Optical remote sensing is an applicable approach for red tide monitoring in wide observation range. This study proposed a red tide identification method using the logical operation of multi-band spectral indices (MBSIs). Five candidate MBSIs from two categories that could potentially indicate red tide outbreaks are selected and integrated into different combinations. The reflectance spectra of red tide measured in the Xinghai Bay, China, are used to determine the optimal combination of MBSIs through the self-organized map network. According to the result, the combination of fluorescence baseline height and the spectral difference indices at red and near-infrared bands achieves the highest accuracy at 0.95 among all the combinations of MBSIs. Therefore, the logical operation of these three MBSIs is applied to Sentinel-2 satellite images to identify red tide in coastal regions. It is found that the logic operation method of MBSIs can work robustly in different sea areas and provides more reasonable results than using any single MBSI. The proposed method is able to detect the red tide that are often undetectable by human eyes with low computational complexity, and can be applied to the rapid detection and daily surveillance on the spatial distribution of red tide outbreaks.

Resistive switching behavior of quasi-2D CsPbBr3 memristors: Impact of ambient atmosphere on logic storage and computing integration with anti-crosstalk and reconfiguration features

Passive units integrating storage and computing with anti-crosstalk and multi-logic reconstruction are crucial for high computing power and high-density non-volatile storage. In this study, we report an anti-crosstalk and reconfigurable logic memory based on a single passive quasi-two-dimensional (2D) CsPbBr3 device. The effect of the ambient atmosphere (air and N2 environments) on the resistive behavior of the memristors is explored. In air, these devices exhibit negative differential resistance (NDR) effects and antipolar resistive switching behavior, while in N2, they display irreversible switching from low-resistance state to high-resistance state. Various active electrodes (Ag, Cu, Au, and C) were employed to investigate this phenomenon. It is proposed that in air, O ions interact with surface defects under high alternating voltage, retaining a significant quantity of Br− ions within the quasi-2D CsPbBr3, resulting in capacitive-like behavior. Conversely, in N2, surface defects capture Br− ions, leading to the absence of a hysteresis loop in the I-V characteristic. Under N2 operation, write-once-read-many (WORM) capability is achieved. Surprisingly, operating under air enables integrated non-volatile storage and computing, facilitating 12 reconfigurable logic operations in a passive 1R structure and suppressing sneak current in crosstalk setups. This study emphasizes the pivotal role of air in the resistive switching mechanism and provides novel insights for developing next-generation memories tailored for high-density integrated circuits and storage-computing integration.

Fully Resistive In‐Memory Cryptographic Engine with Dual‐Polarity Memristive Crossbar Array

AbstractAs data volume and complexity increase, conventional software‐based encryption methods face significant challenges, including vulnerability to attacks and high computational demands. This study proposes a hardware‐based cryptographic engine using a dual‐polarity memristive crossbar array with Ta/HfO2/RuO2 memristors, utilizing stochastic and deterministic operations for enhanced security and efficiency. The system integrates random key generation and XOR‐based logic operations within the memristive array, enabling robust encryption and decryption of binary data with a fully resistive data representation. Experimental validation of alphabet image data encryption and the array scale simulation of individual fingerprint authentication are conducted to validate the robustness of the proposed hardware and cryptographic method. The results demonstrate the potential of the proposed hardware for homomorphic encryption, enabling secure data processing without decryption, which can pave the way for memristive hardware to evolve into resistance‐based digital computing hardware.

SOME CONSTRUCTION METHODS FOR IMPLICATION OPERATORS ON BOUNDED LATTICES

In this paper, we focus the construction methods of implications on bounded lattices. We introduce several methods to obtain implication on bounded lattices. We basically base on implication defined on subinterval such as [a,1] or [0,b] of the bounded lattice L which has a,b ∈ L with a ≤ b for these construction methods. We also use fuzzy logic operators such as t-norms, t-conorms, negations and implications on L in some construction methods. In addition, we give some remarks and examples to make the new construction methods.

Bistable Soft Shells for Programmable Mechanical Logic.

Mechanical computing promises to integrate semiconductor-based digital logic in several applications, but it needs straightforward programmable devices for changing computing rules in situ. A methodology based on strain-governed, bistable soft shells that process digital information by interchanging their internal/external surfaces is proposed. This bistable behavior, explained via model-based design, safeguards robustness by working only once for each input pulse. Thus, these shells are leveraged to create a buffer and a NOT gate that lead to six fundamental gates (AND, OR, NAND, NOR, XOR, and XNOR). All these functions are integrated into a unique programmable device, making mechanically integrated circuits more adaptable with rule-changeable logic operations. This design ensures continuous processes and general applicability to multiple types of signals (a pressurized fluid can replace mechanical driving signals is shown). It also empowers more complex logic functions suitable for expanded applications, such as the half and full adders is addressed.

Dynamically logical modulation for THz wave within a dual gate-controlled 2DEG metasurface.

High-speed logic modulation of terahertz (THz) waves is crucial for future communications, yet a technology gap persists. Here, we report a dual gate-controlled two-dimensional electronic gas logic modulation metasurface that enables symmetric and asymmetric electron distribution states through independent control of the two electron transport channels. The transition between these two states leads to various response modes in the metasurface and notably increases the diversity of the spectrum transformation, resulting in a multivalued relationship in which each output corresponds to more than one input signal, thus establishing the logical modulation. Our results demonstrate the common logical functions of AND, OR, XOR, XNOR, NOR, and NAND at different frequencies with a modulation speed faster than 250 picoseconds. This work offers a unique avenue for the high-speed, free-space logical operation of THz waves and increases the security of secure communication.

Anti-Interference All-Optical Logic Computing Based on a 2D Polarization-Sensitive Photodiode.

Optical logic operation is promising for ultrafast information processing and optical computing due to the high computation speed and low power consumption. However, conventional optical logic devices require either a complex structure and circuit design or a constant voltage supply, which impedes the development of high-density integrated circuits. Here, all-optical logic devices are designed using a self-powered polarization-sensitive photodiode of the GeSe homojunction, which is attributed to an anisotropic band structure and built-in electric field. The single photodiode can realize linear logic functions (AND, OR, NAND) and a nonlinear logic gate (XOR) by programming wavelength, power density, and polarization angle. Moreover, complex logic functions (XNOR, Y = IN1, Y = IN2, Y = IN1, and Y = IN2) can be achieved through integrating two photodiodes in parallel. In addition, the neural network algorithm is utilized to validate the feasibility of all-optical logic computing and anti-interference. This work proposes an avenue to design an all-optical reconfigurable logic operation in polarization-sensitive devices.

A Study of the Optimal Logic Combinations of RO-Based PUFs on FPGAs to Maximize Identifiability.

One of the challenges that wireless sensor networks (WSNs) need to address is achieving security and privacy while keeping low power consumption at sensor nodes. Physically unclonable functions (PUFs) offer a challenge-response functionality that leverages the inherent variations in the manufacturing process of a device, making them an optimal solution for sensor node authentication in WSNs. Thus, identifiability is the fundamental property of any PUF. Consequently, it is necessary to design structures that optimize the PUF in terms of identifiability. This work studies different architectures of oscillators to analyze which ones exhibit the best properties to construct a RO-based PUF. For this purpose, Generalized Galois Ring Oscillators (GenGAROs) are used. A GenGARO is a novel type of oscillator formed by a combination of up to two input logical operations connected in cascade, where one input is the output of the previous operation and the other is the feedback signal. GenGAROs include some previously proposed oscillators as well as many new oscillator designs. Thus, the architecture of GenGAROs is analyzed to implement a GenGARO-PUF on an Artix-FPGA. With this purpose, an exhaustive study of logical operation combinations that optimize PUF performance in terms of identifiability has been conducted. From this, it has been observed that certain logic gates in specific positions within the oscillator contribute to constructing a PUF with good properties, and by applying certain constraints, any oscillator generated with these constraints can be used to construct a PUF with an equal error rate on the order of or below 10-11 using 100-bit responses. As a result, a design methodology for FPGA-based RO-PUFs has been developed, enabling the generation of multiple PUF primitives with high identifiability that other designers could exploit to implement RO-based PUFs with good properties.

Embedding the Calendar and Time Type System in Temporal Type Theory

Temporal Type Theory (TTT) has been recently introduced as a topos-theoretic approach to understanding the behaviour of systems over time. A truly innovative point of TTT is that it makes truth inherently dependent on time; this is to be contrasted with the classical approach in which past, present and future are related via logical operators. Further on this line of research, the notion of truth is substituted by the ‘time duration’ over which a proposition is true, giving rise to the logic of temporal landscapes. In this paper, we embed the main notions of the Calendar and Time Type System (a framework that was built for reasoning about calendric notions in the context of the Web and is centred around the notion of time granularity) in Temporal Type Theory, attempting to address a common requirement in the practical use of temporal formalisms: the ability to speak about certain time moments and appropriate time windows in (past and future) time, in the form of hours, dates, holidays, etc. With a view to concrete applications, we provide examples on how calendar types can be combined with temporal operators of TTT to augment the expressive power of this framework. In that respect, the addition of calendar types genuinely adds to the range of Temporal Type Theory as a powerful specification language.

Aesthetic Constellations of Noah’s Ark

Abstract This article considers Noah’s ark as a motif of the biblical text that travels through numerous other (not least philosophical) discourses. Not only have there been countless references to the motif of the ark in the biblically inspired tradition for centuries, it is also associated with the logical operations of encompassing the dispersed, the entry into reflection, and the aspect of order. The ark functions as a means, a house, a ship, a cave, a living environment, a symbol for language, etc. This article is itself modelled on an illustration in the medieval Beatus super Apocalypsim (The ‘Rylands Beatus’), which depicts the ark as a house of life. The order presented in the illustration suggests possible pathways through the article which leads to alternative ways of reading the contribution.

Gate voltage tuning of photo-responses in n-AlGaAs/GaAs/AlGaAs double-heterojunction

We demonstrate that the gate voltage Vg tunes the Schottky photocurrent ISG for the irradiation of two lights (Light A and B) in an n-AlGaAs/GaAs/AlGaAs double-heterojunction. Light A is a 975-nm laser that illuminates the entire Schottky gate region at 280 μW/mm2. Light B is a 670-nm laser that locally illuminates the ungated region at 0.4 μW. When Vg = 0 V, Light B doubles ISG for Light A. At Vg = 87 mV, ISG is generated only when both Light A and B are irradiated simultaneously, like the logical operation A∩B. When Vg = 165 mV, ISG is induced only for the illumination of Light A alone, like A∩B̄.

Use of artificial intelligence in banknote reconstruction

Banknotes may be damaged during various events, such as floods, fires, insect infestations, and mechanical or manual shredding. Disaster victims might need to perform banknote reconstruction when applying for currency exchange, or investigative agencies might need to conduct such reconstruction during evidence collection. When the number of banknote fragments is small, they can be manually assembled; however, when this number is large, manual assembly becomes increasingly difficult and time-consuming. Therefore, an automated and effective method is required for banknote reconstruction. The process of banknote reconstruction can be considered similar to solving a large-scale jigsaw puzzle. This study employed an artificial intelligence (AI) system to reconstruct damaged banknotes. A robotic arm was used to replace manual separation and automated digital image processing techniques, and AI image registration technology, deep learning, and logical operations were utilized. A deep convolutional neural network was used to estimate the relative homography between images, and fragmented banknotes were mapped to a reference banknote for image transformation, thereby reconstructing the damaged banknotes. Additionally, a repetitive matching method was established to optimize the matching results to achieve the best possible mapping and enhance validation efficiency.