Logic Family Research Articles

Formalized soundness and completeness of epistemic and public announcement logic

Abstract I strengthen the foundations of epistemic logic by formalizing the family of normal modal logics in the proof assistant Isabelle/HOL. I define an abstract canonical model over any set of axioms and formalize completeness-via-canonicity: when the canonical model for the chosen axioms belongs to a certain class of frames, strong completeness over that class follows immediately. I instantiate the result with logics based on various epistemic principles to obtain completeness results for systems from K to S5. I then move to a family of public announcement logics (PAL) and prove abstract results for strong soundness and completeness. I lift the completeness results from epistemic logic to the setting with public announcements in a modular way. This work formulates the completeness-via-canonicity technique as a proper theorem and demonstrates its applicability. Additionally, it succinctly formalizes the requirements for lifting completeness from bare epistemic logic to the addition of public announcements.

Polynomial-time checking of generalized Sahlqvist syntactic shape

The best known modal logics are axiomatized by Sahlqvist axioms, i.e., axioms of a syntactic shape which guarantees these formulas to have such excellent properties as canonicity and elementarity. Recently, the definition of Sahlqvist formulas has been generalized and extended from formulas in classical modal logic to inequalities (sequents) in a wide family of logics known as LE-logics. We introduce an algorithm which checks if a given inequality is generalized Sahlqvist in polynomial time.

Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application

Advances in wearable technology, IoT, and mobile applications have increased the demand for ultra-low-power electronic devices. Adiabatic Logic Circuit (ALC) is a design technique utilized in digital circuits to decrease the power consumption by decreasing the dynamic power dissipation. Current technologies face challenges in achieving both high performance and ultra-low power consumption. This research work introduces a novel approach in digital circuit design, specifically the Gate All-around Carbon Nanotube Field Effect Transistor with Discrepancy Cascode Pass Transistor Adiabatic Logic (GAA-CNTFET-DCPTAL), tailored for ultra-low power applications. This design operates efficiently with a four-phase Power Clock (PC) and demonstrates remarkable performance by achieving operation frequencies of up to 1 GHz while minimizing energy dissipation. GAA-CNTFET provides superior electrostatic control and high carrier mobility, reducing leakage currents and enhancing switching speeds. Simultaneously, Discrepancy Cascode Pass Transistor Adiabatic Logic (DCPTAL) uses adiabatic logic principles and a cascode structure to minimize energy dissipation during switching events. The technology node of proposed model is 10 nm. The software used for assessment is HSPICE is used for the simulation and validation of the proposed design. The proposed GAA-design attains 25.36 %, 14.28 %, and 16.06 % lower average power analyzed with existing techniques, such as Design with Evaluation of Clocked Differential Adiabatic Logic Families for the applications of low Power (DE-CDAL-LPA), Adiabatic logic-base strong ARM comparator for ultra-low power applications (AL-SARM-ULPA) and Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC with Embedded Applications (2PADCL-ULP-VLSI) respectively.

Logic Families

AbstractA logic family is a bunch of logics that belong together in some way. First-order logic is one of the examples. Logics organized into a structure occur in abstract model theory, institution theory and in algebraic logic. Logic families play a role in adopting methods for investigating sentential logics to first-order like logics. We thoroughly discuss the notion of logic families as defined in the recent Universal Algebraic Logic book.

A New Game Theoretic Semantics (GTS-2) for Weak Kleene Logics

AbstractHintikka’s game theoretical approach to semantics has been successfully applied also to some non-classical logics. A recent example is Başkent (A game theoretical semantics for logics of nonsense, 2020. arXiv:2009.10878), where a game theoretical semantics based on three players and the notion of dominant winning strategy is devised to fit both Bochvar and Halldén’s logics of nonsense, which represent two basic systems of the family of weak Kleene logics. In this paper, we present and discuss a new game theoretic semantics for Bochvar and Halldén’s logics, GTS-2, and show how it generalizes to a broader family of logics of variable inclusions.

Hyperarithmetical complexity of infinitary action logic with multiplexing

Abstract In 2023, Kuznetsov and Speranski introduced infinitary action logic with multiplexing $!^{m}\nabla \textrm{ACT}_{\omega }$ and proved that the derivability problem for it lies between the $\omega $ level and the $\omega ^{\omega }$ level of the hyperarithmetical hierarchy. We prove that this problem is $\varDelta ^{0}_{\omega ^{\omega }}$-complete under Turing reductions. Namely, we show that it is recursively isomorphic to the satisfaction predicate for computable infinitary formulas of rank less than $\omega ^{\omega }$ in the language of arithmetic. As a consequence we prove that the closure ordinal for $!^{m}\nabla \textrm{ACT}_{\omega }$ equals $\omega ^{\omega }$. We also prove that the fragment of $!^{m}\nabla \textrm{ACT}_{\omega }$ where Kleene star is not allowed to be in the scope of the subexponential is $\varDelta ^{0}_{\omega ^{\omega }}$-complete. Finally, we present a family of logics, which are fragments of $!^{m}\nabla \textrm{ACT}_{\omega }$, such that the complexity of the $k$-th logic lies between $\varDelta ^{0}_{\omega ^{k}}$ and $\varDelta ^{0}_{\omega ^{k+1}}$.

Microwave-multiplexed qubit controller using adiabatic superconductor logic

Cryogenic qubit controllers (QCs) are the key to build large-scale superconducting quantum processors. However, developing scalable QCs is challenging because the cooling power of a dilution refrigerator is too small (~10 μW at ~10 mK) to operate conventional logic families, such as complementary metal-oxide-semiconductor logic and superconducting single-flux-quantum logic, near qubits. Here we report on a scalable QC using an ultra-low-power superconductor logic family, namely adiabatic quantum-flux-parametron (AQFP) logic. The AQFP-based QC, referred to as the AQFP-multiplexed QC (AQFP-mux QC), produces multi-tone microwave signals for qubit control with an extremely small power dissipation of 81.8 pW per qubit. Furthermore, the AQFP-mux QC adopts microwave multiplexing to reduce the number of coaxial cables for operating the entire system. As a proof of concept, we demonstrate an AQFP-mux QC chip that produces microwave signals at two output ports through microwave multiplexing and demultiplexing. Experimental results show an output power of approximately −80 dBm and on/off ratio of ~40 dB at each output port. Basic mixing operation is also demonstrated by observing sideband signals.

An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.

NbN-based half-flux-quantum element for integration with superconducting qubits

Half-flux-quantum (HFQ) logic is a superconductor logic family comprising conventional Josephson junctions (0-JJs) and π Josephson junctions (π-JJs). The energy scale of HFQ logic can be flexibly reduced by phase shifts owing to π-JJs; thus, HFQ circuits are a promising building block for qubit interface circuits. In this study, we demonstrate an NbN-based HFQ circuit element compatible with NbN-based superconducting qubits for all-NbN monolithic integration of qubits and HFQ circuits. The use of NbN is beneficial for both qubits and HFQ circuits owing to its high-quality junctions and high kinetic inductance. First, we developed a prototype of an NbN-based 0-JJ/π-JJ hybrid fabrication process for designing HFQ circuits. We evaluated 0-JJs and π-JJs fabricated through the hybrid process, which demonstrated that the 0-JJs had a small deviation with regard to critical current density and the π-JJs had a sufficiently high critical current density to work as π phase shifters. Furthermore, we fabricated an HFQ superconducting quantum interference device, which is one of the most fundamental elements in HFQ circuits, and observed clear HFQ-period modulation in the magnetic flux dependence of the maximum current at 4.2 K.

Sequent Calculi for Choice Logics

Choice logics constitute a family of propositional logics and are used for the representation of preferences, with especially qualitative choice logic (QCL) being an established formalism with numerous applications in artificial intelligence. While computational properties and applications of choice logics have been studied in the literature, only few results are known about the proof-theoretic aspects of their use. We propose a sound and complete sequent calculus for preferred model entailment in QCL, where a formula F is entailed by a QCL-theory T if F is true in all preferred models of T. The calculus is based on labeled sequent and refutation calculi, and can be easily adapted for different purposes. For instance, using the calculus as a cornerstone, calculi for other choice logics such as conjunctive choice logic (CCL) and lexicographic choice logic (LCL) can be obtained in a straightforward way.

ONE-VARIABLE FRAGMENTS OF FIRST-ORDER LOGICS

AbstractThe one-variable fragment of a first-order logic may be viewed as an “S5-like” modal logic, where the universal and existential quantifiers are replaced by box and diamond modalities, respectively. Axiomatizations of these modal logics have been obtained for special cases—notably, the modal counterparts $\mathrm {S5}$ and $\mathrm {MIPC}$ of the one-variable fragments of first-order classical logic and first-order intuitionistic logic, respectively—but a general approach, extending beyond first-order intermediate logics, has been lacking. To this end, a sufficient criterion is given in this paper for the one-variable fragment of a semantically defined first-order logic—spanning families of intermediate, substructural, many-valued, and modal logics—to admit a certain natural axiomatization. More precisely, an axiomatization is obtained for the one-variable fragment of any first-order logic based on a variety of algebraic structures with a lattice reduct that has the superamalgamation property, using a generalized version of a functional representation theorem for monadic Heyting algebras due to Bezhanishvili and Harding. An alternative proof-theoretic strategy for obtaining such axiomatization results is also developed for first-order substructural logics that have a cut-free sequent calculus and admit a certain interpolation property.

Design method for unbalanced ternary logic family based on binary memristors

Design method for unbalanced ternary logic family based on binary memristors

Report on “Axiomatizing Conditional Normative Reasoning”

This is a report on the project “Axiomatizing Conditional Normative Reasoning” (ANCoR, M 3240-N) funded by the Austrian Science Fund (FWF). The project aims to deepen our understanding of conditional normative reasoning by providing an axiomatic study of it at the propositional but also first-order level. The focus is on a particular framework, the so-called preference-based logic for conditional obligation, whose main strength has to do with the treatment of contrary-to-duty reasoning and reasoning about exceptions. The project considers not only the meta-theory of this family of logics but also its mechanization.

Design of a Power Efficient Model of PWM Generator for Green Communication using High Performance FPGAs

Aim: This paper will focus on promoting the ideas of green communication Background: Pulse Width Modulation (PWM) generator is used to control the power transfer in any communication model. It is one of the most crucial parts of an electrical circuit. Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication Objective: Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication. Methods: In order to make the PWM suitable for GC, we have implemented the design on VIVADO ISE from Xilinx. The power analysis as well as resource utilization are targeted on three different FPGAs. Results: Different IO standards of Stub Series Terminated Logic (SSTL) family are explored at different FPGA’s. Power analysis is deployed on the 7 series FPGAs of 3 different categories i.e., Spartan 7 (channel length = 28 nm), Kintex 7 (channel length = 20 nm) and ultra scale Zynq 7 (channel length = 16 nm). Conclusion: It can be concluded from power analysis that SPARTAN-7 device is the most powerefficient and ZYNQ Ultra scale+utilizes the highest amount of power. However, KINTEX-7 Ultrascale device lies in the middle of both these devices as far as power consumption is concerned. There is a reduction of 43.07% TP consumption for SPARTAN-7 device with SSTL135 IO when equated with ZYNQ Ultra scale+ with SSTL18_I IO. Also, it can be observed from sections 5.1, 5.2 and 5.3 that there is more contribution of DP in TP consumption than SP. Hence the device utilizes additional power when it is in active state than static state. Since PWM generator is an integral part of data and wireless communication, it should require less power for proficient transmission and wellorganized green computing and communication.

High-density superconductive logic circuits utilizing 0 and π josephson junctions

Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.

Angell and McCall Meet Wansing

In this paper, we introduce a new logic, which we call AM3. It is a connexive logic that has several interesting properties, among them being strongly connexive and validating the Converse Boethius Thesis. These two properties are rather characteristic of the difference between, on the one hand, Angell and McCall’s CC1 and, on the other, Wansing’s C. We will show that in other aspects, as well, AM3 combines what are, arguably, the strengths of both CC1 and C. It also allows us an interesting look at how connexivity and the intuitionistic understanding of negation relate to each other. However, some problems remain, and we end by pointing to a large family of weaker logics that AM3 invites us to further explore.

Voltage-controlled cryogenic Boolean logic gates based on ferroelectric SQUID and heater cryotron

The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process.

Performance Analysis of Hybrid Comparator using 45nm Technology

In the present real-time world, due to the improvements and innovations of System on Chip (SoC) applications, there is a requirement to integrate multiple technology design topologies. The electronic system design is classified as analog, digital, and mixed-signal design. The comparator is the major building block used in the datapath of System on Chip (SoC) application device. The usage of these devices depends on not only functionality but also on the non-functionality parameters considering different performance estimation metrics. The nonfunctional performance metrics for a transistor level design depends on the number of transistors, switching activities of logic level voltages and delay between input and outputs. These performance metrics are improved by considering the multiple logic families for multiple output generations instead of using a single logic family topology. The comparator is the major component in the arithmetic circuits for SoC applications and can be realized by using various design topologies. The vividly used topologies are Conventional CMOS logic, Pass Transistor Logic (PTL), Gate Diffusion Input (GDI) Logic, Stacking technique, Quantum-dot cellular automata, etc. The selection of the design topology for the comparator is made based on the non-functional parameters. The performance of non-functional parameters is improved by combining the topology architectures of different design techniques. In this paper, the comparator is designed using conventional CMOS logic, PTL, GDI, and a hybridized topology for best performance and the same is implemented using 45nm technology. These circuits are designed by using Cadence Virtuoso Electronic Design Automation (EDA) design tools. Non-functional performance parameters are analyzed for different topologies. Index Terms: VLSI Design, Comparator, Datapath, EDA tools, CMOS Logic, GDI Logic, PTL Logic.

A Balanced CMOS Compatible Ternary Memristor-NMOS Logic Family and Its Application

A Balanced CMOS Compatible Ternary Memristor-NMOS Logic Family and Its Application

Some Logics in the Vicinity of Interpretability Logics

In this paper we shall define semantically some families of propositional modal logics related to the interpretability logic \(\mathbf{IL}\). We will introduce the logics \(\mathbf{BIL}\) and \(\mathbf{BIL}^{+}\) in the propositional language with a modal operator \(\square\) and a binary operator \(\Rightarrow\) such that \(\mathbf{BIL}\subseteq\mathbf{BIL}^{+}\subseteq\mathbf{IL}\). The logic \(\mathbf{BIL}\) is generated by the relational structures \(\left<X,R,N\right>\), called basic frames, where \(\left<X,R\right>\) is a Kripke frame and \(\left<X,N\right>\) is a neighborhood frame. We will prove that the logic \(\mathbf{BIL}^{+}\) is generated by the basic frames where the binary relation \(R\) is definable by the neighborhood relation \(N\) and, therefore, the neighborhood semantics is suitable to study the logic \(\mathbf{BIL}^{+}\) and its extensions. We shall also study some axiomatic extensions of \(\mathsf{\mathbf{BIL}}\) and we will prove that these extensions are sound and complete with respect to a certain classes of basic frames. Finally, we prove that the logic BIL+ and some of its extensions are complete respect with the class of neighborhood frames.