Logic Encryption Research Articles

Laponite-activated AIE supramolecular assembly with modulating multicolor luminescence for logic digital encryption and perfluorinated pollutant detection

Recently, the non-covalently activated supramolecular scaffold method has become a prominent research area in the field of intelligent materials. Here, the inorganic clay (LP) promoted the AIE properties of 4,4′,4″,4‴-(ethene-1,1,2,2-tetrayltetrakis(benzene-4,1-diyl))tetrakis(1-ethylpyridin-1-ium) (P-TPE), showing an astonishing 42-fold enhancement of the emission intensity of the yellow-green luminescence and a 34-fold increase of the quantum yield via organic-inorganic supramolecular strategy as well as the efficient light-harvesting properties (energy transfer efficiency up to 33 %) after doping with the dye receptor Rhodamine B. Furthermore, the full-color spectral regulation, including white light, was achieved by adjusting the ratio of the donor to the acceptor component and co-assembling with the carbon dots (CD). Interestingly, this TPE-based non-covalently activated full-color supramolecular light-harvesting system (LHS) could be achieved not only in aqueous media but also in the hydrogel and the solid state. More importantly, this panchromatic tunable supramolecular LHS exhibited the multi-mode and quadruple digital logic encryption property as well as the specific detection ability towards the perfluorobutyric acid and the perfluorobutanesulfonic acid, which are harmful to human health in drinking water. This result develops a simple, convenient and effective approach for the intelligent anti-counterfeiting and the pollutant sensing.

Robust, Ultrafast and Reversible Photoswitching in Bulk Polymers Enabled by Octupolar Molecule Design

AbstractImproving the photoswitching rate and robustness of photochromic molecules in bulk solids is paramount for practical applications but remains an on‐going challenge. Here, we introduce an octupolar design paradigm to develop a new family of visible light organic photoswitches, namely multi‐branched octupolar Stenhouse Adducts (MOPSAs) featuring a C3‐symmetrical A3‐(D‐core) architecture with a dipolar donor–acceptor (D–A) photochrome in each branch. Our design couples multi‐dimensional geometric and electronic effects of MOPSAs to enable robust ultrafast reversible photoswitching in bulk polymers. Specifically, the optimal MOPSA (4 wt %) in commercial polyurethane films accomplishes nearly 100 % discoloration in 6 s under visible light with ∼ 100 % thermal‐recovery in 17.4 s at 60 °C, while the acquired kinetics constants are 3∼7 times that of dipolar DASA counterpart and 1∼2 orders of magnitude higher than those of reported DASAs in polymers. Importantly, the MOPSA‐doped polymer films sustain 500 discoloration/recovery cycles with slow degradation, superior to the existing DASAs in polymers (≤30 cycles). We discover that multi‐dipolar coupling in MOPSA enables enhanced polarization and electron delocalization, promoting the rate‐determining thermal cyclization, while the branched and non‐planar geometry of MOPSA induces large free volume to facilitate the isomerization. This design can be extended to develop spiropyran or azobenzene‐based ultrafast photochromic films. The superior photoswitching performance of MOPSAs together with their high‐yield and scalable synthesis and facile film processing inspires us to explore their versatile uses as smart inks or labels for time‐temperature indicators, optical logic encryption and multi‐levelled data encryption.

Robust, Ultrafast and Reversible Photoswitching in Bulk Polymers Enabled by Octupolar Molecule Design.

Improving the photoswitching rate and robustness of photochromic molecules in bulk solids is paramount for practical applications but remains an on-going challenge. Here, we introduce an octupolar design paradigm to develop a new family of visible light organic photoswitches, namely multi-branched octupolar Stenhouse Adducts (MOPSAs) featuring a C3-symmetrical A3-(D-core) architecture with a dipolar donor-acceptor (D-A) photochrome in each branch. Our design couples multi-dimensional geometric and electronic effects of MOPSAs to enable robust ultrafast reversible photoswitching in bulk polymers. Specifically, the optimal MOPSA (4 wt %) in commercial polyurethane films accomplishes nearly 100 % discoloration in 6 s under visible light with ∼ 100 % thermal-recovery in 17.4 s at 60 °C, while the acquired kinetics constants are 3∼7 times that of dipolar DASA counterpart and 1∼2 orders of magnitude higher than those of reported DASAs in polymers. Importantly, the MOPSA-doped polymer films sustain 500 discoloration/recovery cycles with slow degradation, superior to the existing DASAs in polymers (≤30 cycles). We discover that multi-dipolar coupling in MOPSA enables enhanced polarization and electron delocalization, promoting the rate-determining thermal cyclization, while the branched and non-planar geometry of MOPSA induces large free volume to facilitate the isomerization. This design can be extended to develop spiropyran or azobenzene-based ultrafast photochromic films. The superior photoswitching performance of MOPSAs together with their high-yield and scalable synthesis and facile film processing inspires us to explore their versatile uses as smart inks or labels for time-temperature indicators, optical logic encryption and multi-levelled data encryption.

Recent progress on the construction and application of dithienylethene‐based photochromic AIEgens

AbstractPhotochromic fluorescent materials have rapidly developed as a new class of intelligent materials, offering a unique combination of traditional photochromic and organic fluorescent materials. These materials possess remarkable photoresponsiveness that can be observed by the naked eye and exhibit fluorescence color change. Consequently, they have found widespread applications in various domains, including molecular switches, logic encryption, medical diagnosis and treatment, and biosensors. Among the multitude of photochromic systems, those based on dithienylethenes (DTEs) have garnered significant attention due to their exceptional photochromic efficiency, commendable reversible photoresponse and fatigue resistance, as well as excellent photostability and thermal stability. Nevertheless, these photochromic fluorescent materials continue to grapple with the issue of aggregation‐caused quenching (ACQ), a common problem faced by traditional fluorescent materials. Therefore, the integration of DTE systems with aggregation‐induced emission (AIE) systems presents a promising solution to tackle this predicament, enabling an improved quantum yield for photochromic fluorescent materials in their aggregated state and broadening their range of applications. This review comprehensively summarizes and evaluates the construction strategies and application prospects of DTE‐based photochromic AIE luminogens (AIEgens) in recent years, while also providing an outlook on their future development.

Selective control of donor-acceptor Stenhouse adduct populations with non-selective stimuli

Selective control of donor-acceptor Stenhouse adduct populations with non-selective stimuli

Efficient design and analysis of secure CMOS logic through logic encryption

Untrusted third parties and untrustworthy foundries highlighted the significance of hardware security in the present-day world. Because of the globalization of integrated circuit (IC) design flow in the semiconductor industry, hardware security issues must be taken to prevent intellectual property (IP) piracy. Logic encryption is an efficient method to protect circuits from IP piracy, reverse engineering, and malicious tampering of IC for Trojan insertion. Researchers have proposed many logic encryption methods, which lead to overhead in circuit design parameters such as area, power, and performance. This paper aims to bring a trade-off between these parameters, with security being the main key factor, and ensure the design metrics by proposing a novel transistor-level method of logic encryption for CMOS gates. Experimental results show that, on the usage of proposed encrypted key gates, the design overheads such as area, power, delay, and energy are reduced by an average of 42.94%, 37.37%, 26.79%, and 50.96%, respectively, over the existing logic encryption-based topologies.

A framework for data and device protection on mobile devices using logic encryption

A framework for data and device protection on mobile devices using logic encryption

Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption

Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption

Harnessing molecular isomerization in polymer gels for sequential logic encryption and anticounterfeiting.

Using smart photochromic and luminescent tissues in camouflage/cloaking of natural creatures has inspired efforts to develop synthetic stimuli-responsive materials for data encryption and anticounterfeiting. Although many optical data-encryption materials have been reported, they generally require only one or a simple combination of few stimuli for decryptions and rarely offer output corruptibility that prevents trial-and-error attacks. Here, we report a series of multiresponsive donor-acceptor Stenhouse adducts (DASAs) with unprecedented switching behavior and controlled reversibility via diamine conformational locking and substrate free-volume engineering and their capability of sequential logic encryption (SLE). Being analogous to the digital circuits, the output of DASA gel-based data-encryption system depends not only on the present input stimulus but also on the sequence of past inputs. Incorrect inputs/sequences generate substantial fake information and lead attackers to the point of no return. This work offers new design concepts for advanced data-encryption materials that operate via SLE, paving the path toward advanced encryptions beyond digital circuit approaches.

Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption

Hardware security remains as a major concern in the circuit design ow. Logic block based encryption has been widely adopted as a simple but effective protection method. In this paper, the potential threat arising from the rapidly developing field, i.e., machine learning, is researched. To illustrate the challenge, this work presents a standard attack paradigm, in which a three-layer neural network and a naive Bayes classifier are utilized to exemplify the key-guessing attack on logic encryption. Backed with validation results obtained from both combinational and sequential benchmarks, the presented attack scheme can specifically accelerate the decryption process of partial keys, which may serve as a new perspective to reveal the potential vulnerability for current anti-attack designs.

Resilient and Secure Hardware Devices Using ASL

Due to the globalization of Integrated Circuit (IC) design in the semiconductor industry and the outsourcing of chip manufacturing, Third-Party Intellectual Properties (3PIPs) become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware trojans. To thwart such attacks, ICs can be protected using logic encryption techniques. However, strong resilient techniques incur significant overheads. Side-channel attacks (SCAs) further complicate matters by introducing potential attacks post fabrication. One of the most severe SCAs is power analysis (PA) attacks, in which an attacker can observe the power variations of the device and analyze them to extract the secret key. PA attacks can be mitigated via adding large extra hardware; however, the overheads of such solutions can render them impractical, especially when there are power and area constraints. All Spin Logic Device (ASLD) is one of the most promising spintronic devices due to its unique properties: small area, no spin-charge signal conversion, zero leakage current, non-volatile memory, high density, low operating voltage, and its compatibility with conventional CMOS technology. In this article, we extend the work in Reference [1] on the usage of ASLD to produce secure and resilient circuits that withstand IC attacks (during the fabrication) and PA attacks (after fabrication), including reverse engineering attacks. First, we show that ASLD has another unique feature: identical power dissipation through the switching operations, where such properties can be effectively used to prevent PA and IC attacks. We then evaluate the proposed ASLD-based on performance overheads and security guarantees.

Logic Encryption for Resource Constrained Designs

Logic Encryption is a hardware security technique that protects integrated circuit designs that are fabricated at untrusted pure play foundries from being pirated or maliciously modified. In the technique, logic gates are added to the design that are driven by an added key input bus, such that the correct behavior of the circuit is recovered with only the exact correct key input pattern. However, the power, performance, and area (PPA) cost of implementing logic encryption has often been ignored in the literature in favor of increasing the level of security provided. This has proved to be a significant hurdle in transitioning the method to use in commercial-grade designs and a systematic methodology of constraining the cost of logic encryption is needed. In this paper, we propose a generalized Constraint-Directed Logic Encryption (CDLE) methodology. In CDLE, the potential design space of encrypted versions of a circuit is searched to apply logic encryption under PPA constraints. Two example CDLE methods are proposed. The first is a concurrent tree search method which uses commercial tools to sample designs for their PPA cost and determine the optimal encryption strategy. In this method, PPA cost is accurately analyzed at the cost of heavy runtime. The second is a machine learning approach which estimates the PPA cost to predict the optimal encryption strategy. The machine learning model developed in this work is limited, but the results are promising as a direction for study in logic encryption. Detailed experimental results evaluating both methods are presented.

A Novel Low Complexity Logic Encryption Technique for Design-for-Trust

The outsourcing of several untrusted intellectual property designs makes the development of integrated circuits vulnerable to piracy, overbuilding, reverse engineering, and hardware Trojan (HT). To thwart the hardware-based attacks, several design-for-trust (DFT) techniques are reported in the literature. In this paper, we analyze that the existing methods are inefficient to prevent hardware Trojan attacks and also exhibit significant design overhead. Hence, we propose a novel DFT technique that effectively increases the immunity of design against the Trojan attack while requiring minimal overhead. In the proposed technique, various new light-weight key-gate topologies are proposed that effectively increase the triggering probability of Trojan at the rare-triggered nets by encrypting the design. We also propose a new encryption algorithm that identifies an optimal node using a new metric called vulnerability factor in-order to replace it with the proposed key-gate. Our encryption algorithm significantly reduces the number of vulnerable-nets with minimum replacements. The simulation results show that the proposed key-gates reduce on an average 34.2 percent and 35.1 percent per-gate area and energy respectively over the stack-based key-gates. Finally, our DFT technique gives on an average 94 percent area overhead reduction as compared to the best known DFT technique on the ISCAS-85 benchmarks.

Cryptanalysis of a random number generator based on continuous‐time chaos

This study presents the algebraic cryptanalysis of a continuous-time chaotic random number generator (RNG) based on a Zhongtang chaotic system. The chaos-based RNG provides key values for logic encryption, round key formation and the substitution box (S-box) generation steps in AES (advanced encryption standard). In this study, an attack method is proposed to exploit the weaknesses of the chaos-based RNG used in this cryptographic system. By observing a chaotic state variable and knowing the structure of the target RNG, output bit sequence of the target RNG is reproduced by a clone RNG used in master–slave synchronisation scheme. The feasibility of the attack system is confirmed through simulation and numerical results. Through this attack method, the same S-box parameters and key values can be obtained which can be used for decryption of the proposed encryption algorithm. This study targets a specific continuous-time chaos-based RNG and the associated cryptographic system as a case study. However, the cryptanalysis method described in this study is applicable to any continuous-time or discrete-time chaos-based RNGs. Therefore, this study highlights the security vulnerabilities of chaos-based RNGs and emphasises that deterministic chaos phenomena itself should not be considered as the actual source of randomness.

Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption

Logic encryption has emerged to be a potential solution to the problem of Intellectual Property (IP)-Piracy and counterfeiting. However, in the recent past, several attacks have been mounted on existing logic encryption strategies to extract the secret key. SAT attack, the most predominant one among them, exploits the unprotected Design-for-Testability (DfT) infrastructure as a backdoor to launch attacks on sequential circuits. Protecting the DfT infrastructure is of paramount importance to ensure the security of an Integrated Chip (IC). In this paper, we propose a new logic encryption scheme which dynamically obfuscates the scan operation for an unauthorized attempt of scan access. A detailed security analysis on the proposed secure DfT infrastructure demonstrates its ability to thwart SAT attack without compromising the testability of the design. A methodical key-gate placement strategy enables the proposed scheme to eliminate the leakage of key information through weak key-gate locations, offering protection against path sensitization and logic cone based attacks. Unlike other state-of-the-art SAT preventive schemes, our proposed method does not suffer from poor output corruption, which is a fundamental requirement of a logic encryption scheme.

A framework for data and device protection on mobile devices using logic encryption

A framework for data and device protection on mobile devices using logic encryption

An Enhanced Logic Encryption Method with a Fully Correlated Key Interdependency Block

Logic encryption, as a hardware security technique, can protect integrated circuits (ICs) by inserting additional gates. The inserted gates guarantee that predefined outputs are only generated when correct key inputs are provided, preventing IC counterfeiting, intellectual property (IP) theft, and IC overproduction. To evaluate the logic encryption’s robustness, two major criteria are usually utilized, which are (1) the interdependency between the keys and (2) the output corruption against attacks, including path sensitization attack, SATbased attack, hill-climbing attack, etc. However, the majority of existing logic encryption methods emphasize one criterion over the other. In this paper, an enhanced logic encryption method with a fully correlated key interdependency block is proposed. The method enhances the interdependency of keys and determines the locations of key-gates utilizing a rare node analysis method. Experimental results validate that the proposed method can withstand path sensitization attack and ensure 50% Hamming distance with reasonable design overheads.

Design Protection Using Logic Encryption and Scan-Chain Obfuscation Techniques

Due to increase in threats posed by offshore foundries, the companies outsourcing IPs are forced to protect their designs from the threats posed by the foundries. Few of the threats are IP piracy, counterfeiting and reverse engineering. To overcome these, logic encryption has been observed to be a leading countermeasure against the threats faced. It introduces extra gates in the design, known as key gates which hide the functionality of the design unless correct keys are fed to them. The scan tests are used by various designs to observe the fault coverage. These scan chains can become vulnerable to side-channel attacks. The potential solution for protection of this vulnerability is obfuscation of the scan output of the scan chain. This involves shuffling the working of the cells in the scan chain when incorrect test key is fed. In this paper, we propose a method to overcome the threats posed to scan design as well as the logic circuit. The efficiency of the secured design is verified on ISCAS’89 circuits and the results prove the security of the proposed method against the threats posed.

Enhancements to SAT Attack

Logic encryption is an IC protection technique for preventing an IC design from overproduction and unauthorized use. It hides a design’s functionality by inserting key gates and key inputs, such that a secret key is required to activate the design and make it functioncorrectly. The security of a logic encryption algorithm is evaluated according to the difficulty of cracking the secret key. The state-of-the-art attack method identifies a secret key with a series of SAT-solving calls to prune all the incorrect keys. Although it can break most of the existing logic encryption algorithms within a few hours, we observe that there exist two enhancements for increasing its efficiency. First, we introduce a preprocess to identify and eliminate redundant key inputs and simplify SAT problems. Second, we present a key checking process for increasing the pruned incorrect keys in each SAT-solving iteration. We conducted the experiments on a set of benchmark circuits encrypted by six different logic encryption algorithms. The simulation results show that the enhanced method can successfully unlock 10 benchmark circuits which originally could not be cracked within 1 hour. For all the benchmark circuits, the average speedup is approximately 2.2x in terms of simulation time. Furthermore, a recent logic encryption method locks a design by creating cyclic paths, which can invalidate the SAT-based attack method. We analyze the impact of cyclic paths and propose an enhancement to break the cyclic logic encryption method.

Review on Logic Encryption Strategy Ensuring Key Interdependency

With the globalization of IC outline flow, numerous fables organizations outsource the creation of their plan to off-site foundries. As these foundries may not generally be believed, it brings about security vulnerabilities and dangers, for example, forging, IP theft, figuring out, overbuilding and Hardware Trojans. Logic encryption has developed to be a potential answer for secure the plan against these dangers. It presents some additional equipment (key-gates) into the plan to conceal the usefulness from unapproved clients, utilizing security keys. The areas of addition of key-gates decide the nature of the security gave by the subsequent plan. In this paper, we examined pros and cons of few papers and propose a productive technique to defeat the IP theft