Logic Circuits Research Articles

(Invited) Exciton Dissociation in Mixed-Dimensionality SWCNT-Based Heterojunctions

Quantum-confined semiconductors provide highly tunable optical and electrical properties for a wide variety of emerging applications. Semiconducting single-walled carbon nanotubes (s-SWCNTs) have shown tremendous potential in applications ranging from digital logic, biological imaging, quantum information processing, photovoltaics, and thermoelectric energy harvesting. Energy harvesting applications rely critically upon the creation of tailored interfaces that enable the movement of energetic species (excitons, electrons, holes) in specified directions. In this talk, I will discuss the use of a variety of rationally designed “mixed-dimensionality” heterojunctions between s-SWCNTs and transition metal dichalcogenide (TMDC) monolayers to harvest visible/near-infrared photons and convert these excitations into long-lived charge-separated states. Type-II heterojunctions between s-SWCNTs and TMDCs enable rapid exciton dissociation and microsecond charge-separated state lifetimes. We have developed new TMDC/SWCNT/TMDC trilayer architectures that enable charge transfer cascades for improving charge separation yield and lifetime. These trilayer architectures allow us to probe out-of-plane carrier diffusion in the nanotube layer and the degree to which bound interfacial excitons impact the photophysics in these mixed-dimensionality heterostructures. I will also discuss the methodology by which we attempt to quantify the photoinduced exciton dissociation quantum yields in these nanoscale heterostructures. Using several heterostructure results, we are attempting to narrow in on appropriate ways to quantify the local dielectric constant and exciton size in both the SWCNT and TMDC components, each of which impact the estimated charge carrier yields. Taken together, these studies provide fundamental insights into the links between ground-state thermodynamics and excited-state dynamics for model nanoscale heterojunctions used to harvest solar energy and produce long-lived charge-separated states.

MOFs/MXene nano-hierarchical porous structures for efficient ion dynamics

Nature's various hierarchical structures exhibit exceptional performance in enhancing mass transport. However, how to bionic nano-hierarchical structures to enhance ion dynamics and achieve charge regulation is a significant challenge. Herein, a nano-hierarchical porous hybrid membrane inspired by nature was designed by integrating 1D metal-organic frameworks (MOFs) on the 2D MXene substrate utilizing MOF nanoparticles with tailorable positive and negative surface charges. The synergistic effects of the bioinspired nanohierarchical porous structure and surface charge interactions significantly enhance the performance and stability of the nanoconfined membrane, as corroborated by experimental characterizations and theoretical simulations. As a result, the optimized nanohierarchical porous membrane exhibits high a cation selectivity of 0.95, an outstanding power density of 35.04 W m−2, and excellent stability over one month. Synergizing enhanced mass transport and ion dynamics in nano-hierarchically structured materials with tailored charge improves osmotic power generation efficiency and benefits logic circuits with controlled charge transport.

Advancing Molecular-Scale Logic Devices through Multistage Switching in a Luminescent Bimetallic Ru(II)-Terpyridine Complex.

Stimuli-responsive multistep switching phenomena of a luminescent bimetallic Ru(II) complex are employed herein to fabricate multiple configurable logic devices. The complex exhibits "off-on" and "on-off" emission switching upon alternative treatment with visible and UV light. Additionally, remarkable augmentation of the rate as well as quantum yield of photoisomerization was achieved via the use of a chemical oxidant (Ce4+) as well as a reductant (metallic sodium). Upon exploiting the emission spectral response of the complex, several advanced Boolean logic functions, including IMPLICATION as well as 2-input 2-output and 3-input 2-output complex combinational logic gates, are successfully implemented. Additionally, by utilizing the vast efficacy of Python, a novel "logic_circuit" model is devised that is capable of making accurate decisions under the influence of various input combinations. This model transcends traditional Boolean logic gates, offering flexibility and intuition to design logical functions tailored to specific chemical contexts. By integrating principles of logic circuits with chemical processes, this innovative approach enables structure determination of the chemical states based on input conditions, thereby unlocking avenues for exploring intricate interactions and reactions beyond conventional Boolean logic paradigms.

Air-powered logic circuits for error detection in pneumatic systems

Air-powered logic circuits for error detection in pneumatic systems

ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach

ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach

A highly sensitive ratiometric near-infrared nanosensor based on erbium-hyperdoped silicon quantum dots for iron(Ⅲ) detection

Ratiometric fluorescent detection of iron(Ⅲ) (Fe3+) offers inherent self-calibration and contactless analytic capabilities. However, realizing a dual-emission near-infrared (NIR) nanosensor with a low limit of detection (LOD) is rather challenging. In this work, we report the synthesis of water-dispersible erbium-hyperdoped silicon quantum dots (Si QDs:Er), which emit NIR light at the wavelengths of 810 and 1540 nm. A dual-emission NIR nanosensor based on water-dispersible Si QDs:Er enables ratiometric Fe3+ detection with a very low LOD (0.06 μM). The effects of pH, recyclability, and the interplay between static and dynamic quenching mechanisms for Fe3+ detection have been systematically studied. In addition, we demonstrate that the nanosensor may be used to construct a sequential logic circuit with memory functions.

Boosting selective fusion of protocells with DNA logic circuits for in situ detection of exosomal microRNA

Boosting selective fusion of protocells with DNA logic circuits for in situ detection of exosomal microRNA

New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits

New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits

A 0.037 pJ K2$\text{K}^2$ 338 pW temperature sensor based on dynamic leakage‐suppression logic

AbstractThis letter introduces an ultra‐low‐power temperature sensor utilizing dynamic leakage‐suppression (DLS) logic and thoroughly analyses its working principle. The sensor effectively tackles the weak pull‐up challenge inherent in DLS logic ensuring its compatibility with standard digital logic. By capitalizing on the super cut‐off attribute of DLS logic, the frontend of the sensor achieves ultra‐low power consumption, without compromising on measurement precision or the breadth of the temperature range. The digital part of the proposed utilizes the output frequency of the sensor's frontend as the clock source, in conjunction with an external 50 Hz reference clock, achieving a low overall power consumption. The frontend of the temperature sensor was fabricated using a 180 nm process, occupying a minimal area of 374 . The digital part of the circuit is implemented using FPGA. Following a two‐point calibration and system error removal, the sensor, operating at a supply voltage of 0.8 V, demonstrated a error of across the temperature range of −20 to 125 . At 25 , the resolution figure of merit of the sensor was 0.037 pJ , with a maximum voltage sensitivity of 4.2 .

Enhanced CPU Design for SDN Controller.

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

RNA-based logic for selective protein expression in senescent cells

Cellular senescence is a cellular state characterized by irreversible growth arrest, resistance to apoptosis and secretion of inflammatory molecules, which is causally linked to the pathogenesis of many age-related diseases. Besides, there is accumulating evidence that selective removal of senescent cells can benefit therapies for cancer and fibrosis by modulating the inflammatory microenvironment. While the field of so-called senolytics has spawned promising small molecules and peptides for the selective removal of senescent cells, there is still no effective means to detect senescent cells in vivo, a prerequisite for understanding the role of senescence in pathophysiology and to assess the effectiveness of treatments aimed at removing senescent cells. Here, we present a strategy based on an mRNA logic circuit, that yields mRNA-dependent protein expression only when a senescence-specific miRNA signature is present. Following a validation of radiation-induced senescence induction in primary human fibroblasts, we identify miRNAs up- and downregulated in association with cellular senescence using RT-qPCR. Incorporating binding sites to these miRNAs into the 3’ untranslated regions of the mRNA logic circuit, we demonstrate the senescence-specific expression of EGFP for detection of senescent cells and of a constitutively active caspase-3 for selective removal. Altogether, our results pave the way for a novel approach to execute an mRNA-based programme specifically in senescent cells aimed at their detection or selective removal.

Vertically stacked van der Waals heterostructures for three-dimensional circuitry elements

Two-dimensional (2D) layered materials have been actively explored for electronic device applications because of their ability to form van der Waals heterostructures with unique electronic properties. Vertical integration of atomically thin 2D materials can enable the design of a three-dimensional (3D) circuit which is a promising pathway to continuously increase device density. In this study, we vertically stack 2D materials, such as graphene (Gr), MoS2, and black phosphorus (BP) to build transistors, heterostructure p–n diodes, and 3D logic circuits. The vertical transistors built from MoS2 or BP semiconductor exhibit a good on-off ratio of up to 103 and a high current density of ∼200 Acm−2 at a very small V DS of 50 mV. The Gr/BP/MoS2 vertical heterostructure p–n diodes show a high gate-tunable rectification ratio of 102. Finally, we have demonstrated a 3D CMOS inverter by vertical integration of Gr, BP (p-channel), Gr, MoS2 (n-channel), and a 50-nm-thick gold film in sequence. The ability to vertically stack 2D layered materials by van der Waals interactions offers an alternative way to design future 3D integrated circuits.

A Comprehensive Review of Power Consumption in Digital Logic Circuits at Ultra-Low Subthreshold CMOS Levels

In the anticipated spectrum, a lot of work has gone into managing the trade-offs between power, location, and efficiency in the moderate efficiency, moderate power region. However, research into the extremities of this spectrum remains restricted. In particular, there hasn't been enough research done on the extremes of extraordinarily low power consumption with appropriate efficiency and extraordinary efficiency with energy that is within realistic bounds. In this work, very low subthreshold power levels are used to study the power consumption characteristics of digital logic circuits in static Complementary Metal-Oxide-Semiconductor (CMOS) devices. The study shows that operating transistors below their threshold voltage might result in significant energy savings. This research emphasises the significance of subthreshold design strategies for contemporary electronic circuits that aspire for low-power operation without sacrificing efficiency. The results highlight the potential for significant progress in energy-efficient circuit design and highlight the delicate balance between preserving performance and cutting power usage. As a result, this research adds to our understanding of low-power electronics and provides information that may lead to the development of future technologies that are more efficient and sustainable. Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

Dynamic Power Saving for CMOS Circuits

With more functionalities being integrated into a microchip today, higher processing power is drawn. As a result of this, clock and logic power consumption has turned out to be a critical issue to be coped with by chip designers. In this paper, we present various power-saving approaches employed in complementary metal oxide semiconductor (CMOS) circuit designs. The approaches involve restructuring the logic circuits, performing clock gating, and selecting the appropriate circuits for counters and frequency divisions. In order to show their efficacies in power optimization, the approaches were applied to a phase-locked loop (PLL), clock divider (CD), full adder (FA), counter, arithmetic logic unit (ALU), and microprocessor without interlocked pipelined stages (MIPS) circuits and validated using Intel Quartus Prime Lite and Mentor Graphics Modelsim. The following conclusions can be drawn from the results: Firstly, the efficacy of minimizing power dissipation using logic restructuring is found to be in direct proportion with the rate of the switching activity (SA); secondly, a maximum of 3.5% of thermal power dissipation can be saved using clock gating; thirdly, gray counters give the lowest power consumption; and, finally, the thermal power estimation for the phase-locked loop (PLL) is relatively higher than that for the clock divider (CD) when both of them are implemented for dividing frequencies.

A Review on FPGA-based Architectures for Noise Removal of Digital Images using High-Level Design

Image corruption during the acquisition and transmission operations may be caused by a variety of disturbances. Scientists are still having trouble getting rid of the noise in the original picture. picture denoising is a technique used to improve a picture's visual quality and extract small details from a damaged image. Improving an image to make it crisper than it was originally is the aim of image restoration. The field of image processing is vast. This paper presents the results of some significant work in the subject of image denoising. It looks into image denoising using some of the most recent methods, such as SEPD (Simple Edge Preserved De-noising) and RSEPD (Reduced Simple Edge Preserved De- noising).Image corruption during the acquisition and transmission operations may be caused by a variety of disturbances. Scientists are still having trouble getting rid of the noise in the original picture. picture denoising is a technique used to improve a picture's visual quality and extract small details from a damaged image. Improving an image to make it crisper than it was originally is the aim of image restoration. The field of image processing is vast. This paper presents the results of some significant work in the subject of image denoising. It looks into image denoising using some of the most recent methods, such as SEPD (Simple Edge Preserved De-noising) and RSEPD (Reduced Simple Edge Preserved De- noising). Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

Configurable anti-ambipolar photoresponses for optoelectronic multi-valued logic gates

Anti-ambipolar transistors (AATs) are the leading platform for the paradigm shift from binary to multi-valued logic (MVL) circuits, increasing circuit integration density and data processing capacity. However, most AATs with p–n heterojunctions present limited controllability of the transconductance peak, which is key to MVL operation. Here, we report optically configurable AAT/bi-AAT photoresponses implemented with an InSe field-effect transistor for potential MVL operations. The charge trapping and detrapping processes incorporated with manually introduced trap states form the AAT peaks. Furthermore, leveraging a symmetric device configuration, the dark current is significantly suppressed, and AAT photoresponses are highlighted. Contributed by two pathways of trap states, the AAT/bi-AAT photoresponses are switchable by incident optical wavelength. This dependence facilitates optical wavelength to be one of the logic inputs for MVL, based on which we propose circuit-free ternary logic gates in a single device that can achieve more than ∼6 and ∼19 times improved data density (1 bit per transistor) for NMAX and XNOR, compared with such circuits in a traditional binary design. This work realizes optically controlled AAT photoresponses, paving the way to exploit optical wavelength as a new degree of freedom in MVL computing, offering a route toward ultra-high-density, ultra-low-power, and optically programmable optoelectronic integrated circuits.

A versatile and fast pixel matrix read-out architecture for MAPS

A digital asynchronous logic is proposed as a generic matrix readout for Monolithic active pixel sensors. The architecture is implemented for pixel pitch ranging from 18 to 30µm. Post-layout simulations with realistic hit shapes and rates up to 200MHz/cm2 show that time stamping at the 20ns level can be achieved for a digital power cost below 10mW/cm2.

Blood-based biomemristor for hyperglycemia and hyperlipidemia monitoring

Thanks to its structural characteristics and signal patterns similar to those of human brain synapses, memristors are widely believed to be applicable for neuromorphic computing. However, to our knowledge, memristors have not been effectively applied in the biomedical field, especially in disease diagnosis and health monitoring. In this work, a blood-based biomemristor was prepared for in vitro detection of hyperglycemia and hyperlipidemia. It was found that the device exhibits excellent resistance switching (RS) behavior at lower voltage biases. Through mechanism analysis, it has been confirmed that the RS behavior is driven by Ohmic conduction and ion rearrangement. Furthermore, the hyperglycemia and hyperlipidemia detection devices were constructed for the first time based on memristor logic circuits, and circuit simulations were conducted. These results confirm the feasibility of blood-based biomemristors in detecting hyperglycemia and hyperlipidemia, providing new prospects for the important application of memristors in the biomedical field.

Tunable anti-ambipolar vertical bilayer organic electrochemical transistor enable neuromorphic retinal pathway

Increasing demand for bio-interfaced human-machine interfaces propels the development of organic neuromorphic electronics with small form factors leveraging both ionic and electronic processes. Ion-based organic electrochemical transistors (OECTs) showing anti-ambipolarity (OFF-ON-OFF states) reduce the complexity and size of bio-realistic Hodgkin-Huxley(HH) spiking circuits and logic circuits. However, limited stable anti-ambipolar organic materials prevent the design of integrated, tunable, and multifunctional neuromorphic and logic-based systems. In this work, a general approach for tuning anti-ambipolar characteristics is presented through assembly of a p-n bilayer in a vertical OECT (vOECT) architecture. The vertical OECT design reduces device footprint, while the bilayer material tuning controls the anti-ambipolarity characteristics, allowing control of the device’s on and off threshold voltages, and peak position, while reducing size thereby enabling tunable threshold spiking neurons and logic gates. Combining these components, a mimic of the retinal pathway reproducing the wavelength and light intensity encoding of horizontal cells to spiking retinal ganglion cells is demonstrated. This work enables further incorporation of conformable and adaptive OECT electronics into biointegrated devices featuring sensory coding through parallel processing for diverse artificial intelligence and computing applications.

Electro-optical logics by three-terminal quantum-well-light-emitting transistors integration

The three-terminal quantum-well-light-emitting transistors (QW-LETs) possess appealing characteristics, including multipath bidirectional electrical and optical inputs/outputs, transistor functionalities, and picosecond recombination lifetimes. This article presents the inaugural demonstration of electro-optical sequential logic circuits—first implementations of set-reset (SR) latches. These two latches feature both electrical and optical connectivities through a three-terminal QW-LET platform. Universal gates, such as NOR and NAND logic gates, have been manufactured and showcased, exhibiting accurate logic functionalities. Additionally, we propose two electro-optical SR latches based on NOR and NAND logic gates—the electro-optical registers, serving as fundamental building blocks for more intricate optoelectronic field-programmable gate arrays. The monolithically integrated QW-LET platform holds the potential to offer a comprehensive range of potent building blocks for optoelectronic chips and high-performance optoelectronic computing.