Design Of Logic Cells Research Articles

A Full-Custom Design Flow and a Top-Down RTL-to-GDS Flow for Adiabatic Quantum-Flux-Parametron Logic Using a Commercial EDA Design Suite

The adiabatic quantum-flux-parametron (AQFP) circuit is a superconductor digital logic family with extremely low power consumption. It consumes five orders less power than the state-of-the-art CMOS circuits and three orders of magnitude less power than RSFQ circuits, another competing digital superconductor technology. The computing resources required by society are increasing every year, and the AQFP circuit is a strong candidate for the next generation of computers. In previous research, a 4-bit MANA microprocessor and a 16-bit Kogge-Stone adder using AQFP logic were designed and demonstrated. These circuits were designed almost by hand, and the development environment needs to be improved to implement AQFP circuits for practical applications. So, we used Synopsys EDA tools typically used for CMOS design to create a full-custom design flow for logic cell design and a top-down flow to design combinational logic circuits automatically. We integrated a circuit design editor with simulation and verification tools for the full-custom design flow. For the top-down flow, we created an environment that automatically performs logic synthesis, path balancing, cell placement, and signal and excitation routing. 1024-bit adders with more than two million Josephson junctions (JJs) have been successfully designed.

Efficient logic cell design for ultralow-energy subthreshold operation in wearable biomedical systems

This paper explores efficient logic cell design strategies for ultralow-energy subthreshold operation in wearable biomedical systems. Traditional logic cell design approaches often lead to suboptimal efficiency due to unbalanced Pull-Up (PU) and Pull-Down (PD) networks. Various techniques are examined, including balanced PU/PD network design using body biasing and statistical distribution analysis of drain-source current. Moreover, the reverse channel (RSC) effect is investigated for device optimization. Single-stage gates such as inverters, NAND, and NOR gates are designed with Mentor Graphics tools to minimize power dissipation and area. Multistage gates like XOR and XNOR gates are also optimized for reduced signal propagation delay. A detailed analysis of D-flip-flop designs with varying transistor counts is presented. Power dissipation, delay, rise time, and fall time characteristics are compared for flip-flop configurations comprising 18, 10, and 5 transistors. The results indicate significant energy optimization with the proposed designs, particularly with the 5-transistor configuration, demonstrating the effectiveness of the proposed methodologies in achieving superior energy efficiency and reduced signal noise in biomedical systems.

Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design

To sustain transistor scaling beyond lateral 7 nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. To overcome the roadblocks of logic cell design using this emerging technology, this work explores compact modeling of 3D GAA-JLNTs based on physics of junctionless transport. The model features an explicit continuous analytical form of drain current calculations adapted for a 14 nm channel junctionless nanowire transistor (JLNT) technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary simulations have been explored for performance assessment of logic circuits, such as inverters with passive load, active load and complementary topologies as well as ring oscillators, designed using the developed JLNT compact model.

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

Routing closure and design-for-manufacturability (DFM) challenges exacerbate nonrecurring engineering (NRE) costs, a steep barrier to entry for advanced sub-20-nm CMOS nodes, making low-volume fabrication of integrated circuits (ICs) almost intangible. For ICs in which the cost of design dominates the fabrication, we seek to trade some amount of chip area to lower NRE costs. To this end, we consider designing logic cell layouts for easier routing and DFM closure. We accustom a layout simplification and reuse approach to build standard cell libraries such that good pin access and layout regularity are ensured for all cells. Using a commercial 14-/16-nm technology, we developed two 100-cell logic cell libraries that are, respectively, 9 and 10.5 metal tracks tall. Our routing experiments on multiple designs show that taller cells can endure 20% higher placement density while reducing the number of design rule check (DRC) violations by four orders of magnitude compared with a commercial 7.5 track library. Silicon measurements show that taller cells can enable faster design closure in ICs with stringent performance requirements at the cost of a marginal power overhead. Finally, our logic cell design approach can make advanced CMOS nodes more affordable for low-volume design.

A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements

A ViaLink TM programming element, which forms a metal-to-metal link when programmed, has been incorporated in a CMOS field programmable gate array. The low impedance and small physical size of the ViaLink, combined with an innovative logic cell design, result in an FPGA with very high speed, high density, and low power consumption. Advanced CAE design tools permit fast implementation of high gate utilization designs with logic functions operating at speeds in excess of 100 MHz. This paper describes the logic cell structure, interconnect architecture, performance characteristics and CAE tools developed for the QL8 × 12, the first member of a family of high-speed FPGAs.