Logic Capacity Research Articles

Showing, Not Saying, Negation and Falsehood: Establishing Kimhi’s Two-Way Logical Capacities with Wittgenstein’s Samples

Recently, Irad Kimhi has argued that negation and falsehood can be made intelligible by understanding assertions/judgements as acts of two-way logical capacities. These are capacities that are, at the same time, for (1) positive and negative assertions/judgements and (2) positive and negative facts. Kimhi’s account of negation and falsehood, however, faces severe problems. I argue that these problems can be resolved, and that a new understanding of cases of negation and falsehood can be achieved, by regarding two-way logical capacities for assertion/judgement and facts as established and undergirded by what Ludwig Wittgenstein calls “samples”. The standard metre sample, for instance, establishes and undergirds the capacity for asserting that something, x, is one metre long (meaning: x is like the standard metre in length). At the same time, it establishes and undergirds the capacity for the fact that x is one metre long (when x is like the standard metre in length). As I explain, invoking samples means we cannot say, as Kimhi wants to, what assertion/judgement, negation, and facts, in general, are but can only show what they are, one case at a time. This, however, is a boon not a disadvantage.

Analytical Placement with 3D Poisson’s Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs

As design complexity keeps increasing, the 2.5D field-programmable gate array (FPGA) with large logic capacity has become popular in modern circuit applications. A 2.5D FPGA consists of multiple dies connected through super long lines (SLLs) on an interposer. Each die contains heterogeneous logic blocks and ASIC-like clocking architectures to achieve better skew and timing. Existing works consider these problems separately and thus may lead to serious timing issues or routing failure. This article presents an analytical placement algorithm for the 2.5D FPGA to simultaneously minimize the number of inter-die SLL signals and intra-die clocking violations. Using a lifting dimension technique, we first formulate the 2.5D global placement problem as a three-dimensional continuous and differential minimization problem, where the SLL-aware block distribution is modeled by 3D Poisson’s equation and directly solved to obtain an analytical solution. Then, we further reformulate the minimization problem as a separable optimization problem with linear constraints. Based on the proximal alternating direction method of multipliers optimization method, we efficiently optimize the separable subproblems one by one in an alternating fashion. Finally, clock-aware legalization and detailed placement are applied to legalize and improve our placement results. Compared with the state-of-the-art works, experimental results show that our algorithm can resolve all clocking constraints and reduce the number of SLL crossing signals by 36.9% with similar wirelength in a comparable running time.

The reemergence of the language-of-thought hypothesis: Consequences for the development of the logic of thought.

Quilty-Dunn et al. defended the reemergence of language-of-thought hypothesis (LoTH). My commentary builds up implications for the study of the development of our logical capacities. Empirical support for logically augmented LoT systems calls for the investigation of their logical primitives and developmental origin. Furthermore, Quilty-Dunn et al.'s characterization of LoT helps the quest for the foundation of logic by dissociating logical cognition from natural language.

Prospects for using soft processors in systems-on-a-chip based on field-programmable gate arrays

Objectives. Developing the element base of field-programmable gate arrays (FPGA) may significantly affect the design of electronic devices due to the enhanced logical capacity of such chips and the general tendency towards increased subsystem integration. The system-on-a-chip (SoC) concept is aimed at combining receiving, processing, and exchange subsystems onto a single chip, as well as at implementing control, diagnostic, and other auxiliary subsystems. The study aimed at developing a method for soft processor applications, i.e., processors based on configurable logical resources, for implementing control functions in an FPGA-based SoC.Methods. A digital system design methodology was used.Results. For soft processors, a unified design route based on selecting architectural parameters qualitatively corresponding to control tasks was considered. In particular, such parameters as instruction set addressness, number of pipeline cycles, and arithmetic logic unit configuration are adjustable at the design stage to allow the optimization of the soft processor in the discrete parameter space. An approach to rapid prototyping of the assembler based on stack-oriented programming language with regular grammar was also considered. The control of digital signal processing hardware as part of an SoC is the promising application area for soft processors. An implementation is considered on the example of an SoC based on Xilinx Virtex-7 FPGA containing several processor cores developed using the proposed methodology.Conclusions. The considered approaches to soft processor design allow the rapid prototyping of the control processor core for operation as part of an FPGA-based SoC.

The effect of gate voltage boosting on the power efficiency of multi-context FPGAs

Gate voltage boosting has been routinely used in FPGAs to increase the performance and energy efficiency of pass transistor circuits. The boosting technique is used either alone or in conjunction with level restorers to restore pass transistor outputs to the supply voltage level, which can lead to significant improvement in the power-delay product. Gate voltage boosting is achieved in conventional FPGAs by powering the configuration memory with the boosted voltage and boosted data coming from the configuration memory is directly applied to the gates of the routing multiplexers. In multi-context FPGAs, however, configuration memory data need to pass through the context switches before it can be applied to the routing multiplexers. Passing boosted signals through the context switches can result in significantly higher power consumption, which can be a major concern in multi-context FPGAs. As a result, this work investigates the removal of gate voltage boosting from FPGAs and compares the energy efficiencies of the boosted FPGAs and FPGAs without boosting for multi-context FPGAs. We found that if frequent content switching is required then non-boosted multi-context FPGAs with a larger number of configuration contexts achieve lower power-delay-product compared to boosted multi-context FPGAs. In particular, for single-context FPGAs, boosted FPGAs have 15%–65% lower power-delay product than FPGAs without boosting. Boosted multi-context FPGAs maintain this advantage if the context switching is done infrequently. This advantage, however, reduces if the context switching is done more frequently and, at the same time, boosted FPGAs also become less efficient in terms of power-delay-product as the number of configuration contexts is increased. For ten configuration contexts, FPGAs without boosting can achieve 2%–35% lower power-delay product compared to boosted FPGAs if the context switching is performed every clock cycle and this advantage continues to rise as the number of configuration contexts is increased. Furthermore, FPGAs without boosting also have the advantage of achieving higher logic capacity compared to boosted FPGAs. Under the same power budget, for ten configuration contexts, FPGAs without boosting achieve 1.2–2 times higher logic capacity compared to boosted FPGAs.

ВОСЬМИЭЛЕМЕНТНЫЕ ЦИКЛЫ ТВОРЕНИЯ И АЛГОРИТМЫ ХУДОЖЕСТВЕННОГО ПОВЕСТВОВАНИЯ: ГЕНЕЗИС И РАЗВИТИЕ ОТ ЧАСТНОГО К ОБЩЕМУ

Some linguists pay attention to the logical capacity and integrity of the eight-element structures. This is confirmed by the musical syntax and the system of modal organization. The author of the article draws on the analysis of creation myths, ancient antique and Chinese ontological models, the concept of poetic experiences of ancient Indian poetics. The purpose of the study is to establish by means of humanitarian research the general patterns of development and selforganization. The description takes into account the line of narration, following in the direction from the particular to the general (counterclockwise) and the line of genesis (clockwise). The development from the general to the particular (the line of genesis) reflects the aspects of other reality containing the historical context, mystical experiences, subjective perceptions, help. The line of genesis follows from the 1st text unit (symbolic North-West) and leads to the maximum disclosure of the central image in the 8th (symbolic West). The development from the particular to the general (also from the northwestern sector) reflects the stages of the formation of the main character (the Duad phase), realizing the opposite direction of the model.

Strictures on an Exhibition

In Grundgesetze der Arithmetik, Frege tried to show that arithmetic is logical by giving gap-free proofs from what he took to be purely logical basic laws. But how do we come to judge these laws as true, and to recognize them as logical? The answer must involve giving an account of the apparent arguments Frege provides for his axioms. Following Sanford Shieh, I take these apparent arguments to instead be exhibitions: the exercise of a logical capacity in order to bring us into a state of judgement. I provide an account of what sort of inferential capacities are at play in such exhibitions, and explain how they lead us to judge that Frege’s primitive laws are general and undeniable. I will also situate my account with respect to other rival interpretations, particularly the elucidatory interpretations of Joan Weiner and Thomas Ricketts.

Iot Cloud Convergence, Emerging Economy And Development Issues

The Internet of Things is an emerging subject of technical, social, as well as likewise economic worth. Buyer items, durables, autos and also vehicles, commercial and additionally energy parts, sensing units, along with various other everyday things are being mixed along with Internet hookup and strong info logical capacities that ensure to enhance the method our teamwork, life and play. This paper provides the detailed information about IoT cloud convergence, emerging economy and development issues.

Iot Cloud Convergence, Emerging Economy And Development Issues

The Internet of Things is an emerging subject of technical, social, as well as likewise economic worth. Buyer items, durables, autos and also vehicles, commercial and additionally energy parts, sensing units, along with various other everyday things are being mixed along with Internet hookup and strong info logical capacities that ensure to enhance the method our teamwork, life and play. This paper provides the detailed information about IoT cloud convergence, emerging economy and development issues.

ANALYSIS OF J. KEYNES'S CONTRIBUTION IN THE DEVELOPMENT OF ECONOMIC THEORY

The article describes the educational and scientific university environment in which Keynes's talent was formed, as well as the Bloomsbury Circle of Intellectuals, in which Keynes occupied a prominent place. The formation of Keynes's specific approach to economic problems, which combine the analysis of real problems, theory and formulation of the practical proposals, is considered on the example of the early work of Keynes in the 1910s. The article argues that Keynesianism is the real engine of the modern economy. Keynes developed methods and apparatus by which the conceptual vision of economics is transformed into concrete representations of the economic theory. After a long journey, shown in his works ("General Theory of Employment, Interest and Money"), Keynes developed his vision of economic and social phenomena as an analytically functional analysis, and finally destroyed the logical capacity of people's faith in the ability of a free market economy to automatically maintain full employment, identified the possibility of influencing the regulation of money circulation on prices, exports, imports, production process and employment. Despite criticism of his theoretical evidence, even his opponents agreed that Keynes's ideas had been confirmed in practice. At the end of the article are the assessments of Keynes' research by authors and scientists with different views.

Designing efficient FPGA tiles for power-constrained ultra-low-power applications

High power consumption of Field-Programmable Gate Arrays (FPGAs) makes them a less attractive choice for ultra-low-power applications. Depending on the power source, ultra-low-power systems could either be constrained by power (energy harvesting systems) or by energy (battery-powered systems). In this work, we are evaluating four different FPGA tiles to find the one that is better suited for both power-constrained and energy-constrained systems. Ultra-low-power systems apply voltage downscaling to reduce the power consumption. However, the operational limits of different blocks do not allow conventional FPGA to be operated at very low voltage. Therefore, their logic capacity can only be increased by 2–4 times by applying voltage downscaling. In this work, we identified the blocks in FPGA tiles that are vulnerable at low voltage and replace them with alternate circuits. The results indicate that, by slight modifications in the conventional FPGA tiles, logic capacity can be increased up to 8 times, whereas power-delay-product can be reduced up to 74%.

Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os

As 2.5-D field-programmable gate arrays (FPGAs) have larger logic capacity and higher pin counts compared to conventional FPGAs, they are already deployed in some multi-FPGA systems. 2.5-D FPGA consists of multiple dies connected through an interposer. Since the interposer provides only a fraction of the amount of interconnect resources with an increased delay compared to that within individual dies, it is important to reduce the number of signal crossings between dies both for routability and timing consideration when a circuit is mapped to a 2.5-D FPGA. In a multi-2.5D FPGA system with time-multiplexed hardwired inter-FPGA connections, there can be tens of thousands of inter-FPGA signals incident with each FPGA and their pin assignment can greatly affect the amount of die-crossing signals within the FPGAs. In this article, we formulate the pin assignment problem for such systems with the objective of minimizing signal crossings between dies within the individual FPGAs. Taking into consideration of the multi-die structure of 2.5-D FPGA, we propose two different iterative refinement approaches to the problem, one based on integer linear programming (ILP) and the other algorithm C-2MCF based on clustering optimization and minimum cost flow optimization. Compared to a greedy pin assignment heuristic for minimization of signal crossings between dies, C-2MCF produced 27.1% less crossings on average. While the ILP-based algorithm has up to 1% quality advantage over C-2MCF for moderate-sized instances, C-2MCF is orders of magnitude faster and can comfortably handle very large problem instances. In addition, the proposed minimum cost flow techniques within C-2MCF can also be used in conjunction with any other possible pin assignment method to enhance the final result.

АДАПТИВНОЕ УСТРОЙСТВО ПРЕДЫСКАЖАЮЩЕЙ ЛИНЕАРИЗАЦИИ ДЛЯ БОРТОВЫХ РАДИОПЕРЕДАЮЩИХ УСТРОЙСТВ.

The improvement of energetic and spectral characteristics of the satellite transmitters which act in the harsh space environment with the help of the predistortion linearization becomes more and more actual task. The proposed adaptive predistortion device is based on the correlation evaluation of the nonlinear distortion level at the output of the power amplifier. The device allows to provide more effective linearization in the conditions with changing characteristics of the satellite transmitter within the lifetime of the satellite at the orbit in difference to the systems with advance tuning. The proposed technical solution has a higher reliability and simplified technical implementation in comparison with the analogs due to lack of the preliminary analog and digital processing of the RF signal. The simplified algorithm which requires lesser logical capacity in the digital microcircuits than conventional adaptive algorithms was developed for the modeling of the adaptive predistortion device. The proposed algorithm of changing the parameters of the predistortion linearizer requires less mathematical calculations within one iteration cycle, which is based on the determination of the cross-correlation function gradient rise direction. The obtained results of proposed predistortion linearizer modeling show that the process of two-dimension adaptation based on the developed algorithm is monosemantic and leads to the recovery of the linearizer’s non-linear characteristics optimal tune. The adaptation process leads to the lowering of the intermodulation distortion at the output of the power amplifier in a few adaptation cycles. It is worth noting that the process of the optimization and selection of the two parameters of the predistortion linearizer in the amplifier flows the same way whatever if the analog of digital implementation of the linearizer is used.

Image Edge Detectors under Different Noise Levels with FPGA Implementations

The process to locate objects in an image passes through different phases. At the forefront of these phases, and most importantly, is the edge detection. If edges in an image are identified accurately, all of the objects will be located correctly for further processing phases. Noisy images contain high-frequency contents which might be interfered with image edges that makes edge detection more difficult. In this paper, a software comparative analysis of the performance of three different edge detectors, namely, Roberts, Prewitt and Sobel, is presented. The comparative analysis is performed to check the performance robustness of the edge detectors when noise level fluctuates in the image. In addition, an embedded hardware (HW) system is developed to implement the three detectors on the Zedboard FPGA prototyping board. The purpose of this implementation is to have an embedded system for on-the-move applications where portability is desired. To exploit the new features of the Xilinx Zynq-7000 series, we partition the implementation into (1) hardware part (running on logic gates of FPGA) and (2) software (SW) part (running on ARM processor of FPGA). This heterogeneous HW/SW implementation allows for high accurate results with high speed and efficient area. Furthermore, a hardware comparative analysis of the speed and area of the detectors is presented. The evaluation is performed by using different images (with their ground truths) downloaded from the BSDS500 dataset. The tools used for FPGA implementation are MATLAB and Microsoft Visual Studio (as software tools), Vivado High-level synthesis (HLS) and Software Development Kit (SDK) (as hardware tools). The experimental results show that the Roberts detector achieves better edge detection when the noise level is higher than 40%. It is also faster and requires less capacity of logic gates among the other detectors employed in this study.

Assessment of a block curriculum design on medical postgraduates\u2019 perception towards biostatistics: a cohort study

BackgroundBiostatistics is a key but challenging subject in medical curricula that is usually delivered via a didactic approach in China. However, whether it is the best teaching approach to improve the learner’s competency, especially for medical postgraduates is yet to be proved. Therefore, a block curriculum design was initially developed to provide selective education to the postgraduates towards the professional career of their interest. A questionnaire was designed to assess the students’ perceptions toward biostatistics as these affective factors might impact the learning process. Thus, the present study aimed to detect whether the new block curriculum design could promote the students’ positive perceptions and further improve the course achievement.MethodsThis cohort study investigated and assessed the perceptions toward biostatistics of the first-year postgraduates undergoing traditional teaching and block teaching, respectively. Structural equation modeling was applied to explore the association between perception and course achievement in the block teaching group.ResultsWith a response rate of 97.84 and 96.67% from the two cohorts respectively, 499 block teaching postgraduates had more positive perceptions as compared to 465 traditionally teaching postgraduates with Likert 5-point agreement response mean of 3.50 vs. 3.31 for course value, 3.66 vs. 2.97 for course comment, and 4.29 vs. 4.10 for expectation. Moreover, block teaching students presented superior confidence about academic statistical knowledge, and therefore, 77.96% of them approved of the new teaching approach. Age, specialty, research experience, logical thinking capacity, mathematical basics, and computer basics might influence the postgraduates’ self-assessment ability (all P < 0.05). Structural equation modeling confirmed a positive correlation between perceptions and the course achievements with a reasonable fit.ConclusionsThe block curriculum design in the biostatistics course improved the postgraduates’ positive perception and may have had a positive role in improving postgraduates’ achievement in learning biostatistics.

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC

This paper proposes a SAT-based formulation to evaluate the logical capacity of VIA-configurable block templates. The proposed solution is able to support any user-defined regular layout. The proposed SAT formulation was sucessufully applied to the three main VCSA fabrics in the literature considering transistor networks from an open cell library and transistor networks representing all 4-input Boolean functions. We observed that the number of literals and variables in the SAT formulation grows nearly quadratically with respect to the number of transistors in the VCSA fabric. We also noticed that the average runtime of the SAT solver presents a strong dependence on the input VCSA fabric.

LUT based realization of fixed-point multipliers targeting state-of-art FPGAs

Look-up tables (LUT) form the basic logic elements in a large class of modern day field programmable gate arrays (FPGA). With FPGAs increasingly being used in low and medium volume productions, many vendors have improved the capacity and versatility of these devices. The enormous logic capacity inherent in state-of-art FPGAs has made it essential to develop automated computer aided design (CAD) support for logic synthesis using these platforms. Since design entry is the only manual phase in the FPGA CAD-flow, it essentially rules out any scope for technology-dependent optimization, which focusses on achieving optimal mapping of logical functionalities onto the target platforms. Evidently, majority of the work related to the implementation of different arithmetic circuits on FPGAs focuses only on the technology-independent optimizations, where the design process consists of modifying the architecture at the top level without giving any consideration to the mapping of the architecture onto the FPGA device. In this paper, we consider the technology-dependent optimization of the fixed-point bit-parallel multipliers on LUT based FPGAs. Our approach re-structures the initial Boolean network and transforms it into an optimized LUT netlist prior to the design entry phase. The design entry of the optimized netlist is then carried out using instantiation based coding styles. This ensures that the optimizations done prior to the design entry phase remain preserved throughout the synthesis process. We particularly focus on 6-input LUTs that are inherent basic logic elements in state-of-art FPGAs. Theoretical analysis and detailed experimentation using state-of-art Xilinx 7th generation FPGAs reveal a substantial speed-up in performance.

A New Efficient Hybrid Intelligent Model for Biodegradation Process of DMP with Fuzzy Wavelet Neural Networks

A new efficient hybrid intelligent approach based on fuzzy wavelet neural network (FWNN) was proposed for effectively modeling and simulating biodegradation process of Dimethyl phthalate (DMP) in an anaerobic/anoxic/oxic (AAO) wastewater treatment process. With the self learning and memory abilities of neural networks (NN), handling uncertainty capacity of fuzzy logic (FL), analyzing local details superiority of wavelet transform (WT) and global search of genetic algorithm (GA), the proposed hybrid intelligent model can extract the dynamic behavior and complex interrelationships from various water quality variables. For finding the optimal values for parameters of the proposed FWNN, a hybrid learning algorithm integrating an improved genetic optimization and gradient descent algorithm is employed. The results show, compared with NN model (optimized by GA) and kinetic model, the proposed FWNN model have the quicker convergence speed, the higher prediction performance, and smaller RMSE (0.080), MSE (0.0064), MAPE (1.8158) and higher R2 (0.9851) values. which illustrates FWNN model simulates effluent DMP more accurately than the mechanism model.

A collision management structure for NoC deployment on multi-FPGA

With the increasing complexity of algorithms and new applications, the design of efficient embedded systems has to integrate efficient communication structures such as Network-on-Chip. Multi-FPGA platforms are considered to be the most appropriate experimental way to emulate and evaluate these large System-on-Chips. The deployment often goes through the Network-on-Chip partitioning on all FPGAs requiring the use of inter-FPGA communication links between routers. The number of external links and their performance restrict the communication bandwidth. Currently, the number of inter-FPGA signals is considered to be a major problem in the Network-on-Chip deployed on multi-FPGAs. As there are more signals to be connected than IOs, inter-FPGA links must be shared between routers leading to significant bottlenecks. As the ratio of the logic capacity to the number of IOs rises slowly for each FPGA generation, this technological bottleneck will be remaining for future system designs.In this paper, we propose a novel architecture for inter-FPGA collision management in the Network-on-Chip partitioned on multi-FPGAs. The structure ensures to efficiently share the external link between several routers with a minimum number of collisions and inter-FPGA bottlenecks. The proposed architecture is easily placed between the Network-on-Chip and the external protocol. The collision management architecture is based on the BackOff algorithm used in Wi-Fi communications and adapted to FPGA platforms. This algorithm balances accesses among all the routers connected with the inter-board interfacing, thereby avoiding collisions. We compare this structure with traditional techniques using experimental and theoretical results. The novel inter-FPGA architecture for the Network-on-Chip based on the BackOff algorithm achieves lower latency with fewer resources compared to other solutions.

On the Functions of Stylistic Devices in Newspaper Texts (Anaphora and Parallel Syntax)

The article observes the functions of two stylistic devices in modern newspapers. The author studies how the functions of anaphora and parallel syntax depend on their structures and lexical stylistic composition. The analysis of the syntactic structure of each figure is based on the theory of lexical meaning and componential structure of the connotation of stylistic devices. The author reveals the system-semantic relationship between the structural components of the stylistic devices in question, and analyses how the functions of stylistic figures depend on the lexical stylistic content of its speech realization. The author concludes that the logical realization and function of expressive stylistic figures depend on the typical logical-linguistic relationships between the components of constructed speech in the stylistic figures. The logical capacity of anaphora and parallel syntax is caused by the semantic relationship of the repeating units, which form a coherent syntactic structure. An expressive effect is created by repeating an element or repetition in general. The article points out that the aforementioned functions may often be combined with one of them dominating. The author argues that there is a tendency for anaphora and parallel syntax to be used together along with other stylistic devices. As a result, the analysis clarifies the application of stylistic devices.