A collision management structure for NoC deployment on multi-FPGA

Abstract

With the increasing complexity of algorithms and new applications, the design of efficient embedded systems has to integrate efficient communication structures such as Network-on-Chip. Multi-FPGA platforms are considered to be the most appropriate experimental way to emulate and evaluate these large System-on-Chips. The deployment often goes through the Network-on-Chip partitioning on all FPGAs requiring the use of inter-FPGA communication links between routers. The number of external links and their performance restrict the communication bandwidth. Currently, the number of inter-FPGA signals is considered to be a major problem in the Network-on-Chip deployed on multi-FPGAs. As there are more signals to be connected than IOs, inter-FPGA links must be shared between routers leading to significant bottlenecks. As the ratio of the logic capacity to the number of IOs rises slowly for each FPGA generation, this technological bottleneck will be remaining for future system designs.In this paper, we propose a novel architecture for inter-FPGA collision management in the Network-on-Chip partitioned on multi-FPGAs. The structure ensures to efficiently share the external link between several routers with a minimum number of collisions and inter-FPGA bottlenecks. The proposed architecture is easily placed between the Network-on-Chip and the external protocol. The collision management architecture is based on the BackOff algorithm used in Wi-Fi communications and adapted to FPGA platforms. This algorithm balances accesses among all the routers connected with the inter-board interfacing, thereby avoiding collisions. We compare this structure with traditional techniques using experimental and theoretical results. The novel inter-FPGA architecture for the Network-on-Chip based on the BackOff algorithm achieves lower latency with fewer resources compared to other solutions.