Logic Arrays Research Articles

Approaches to Extend FPGA Reverse-Engineering Technology from ISE to Vivado

SRAM-based FPGA(Field Programmable Logic Arrays) requires external memory since its internal memory gets erased when power is cut off. The process of transmitting the circuit netlist in bitstream from external memory during power-up in FPGA is vulnerable to malicious attacks such as bitstream theft and tampering. Previous FPGA reverse-engineering methods focus on FPGAs, supported by ISE (ISE Design Suite). This is because ISE provides XDLRC (Xilinx Design Language Routing Configurable logic) and XDL (Xilinx Design language) files, which are essential for reverse engineering. However, Vivado Design Suite (Vivado) does not offer those files, making it impossible to extend the coverage of reverse engineering to the FPGAs supported by Vivado. In this paper, we propose a method to generate XDLRC and XDL through Vivado. According to experimental results, the XDLRC and XDL generated through Vivado, respectively, match 99% and 75% with those generated in ISE for Artix-7 100T. As a result, this paper has expanded the scope of reverse engineering from being mainly focused on ISE to now also include Vivado. It is important to note that this paper does not encourage bitstream attacks through reverse engineering but rather highlights the risk associated with malicious attacks and emphasizes the importance of security.

Design of a Power Efficient Model of PWM Generator for Green Communication using High Performance FPGAs

Aim: This paper will focus on promoting the ideas of green communication Background: Pulse Width Modulation (PWM) generator is used to control the power transfer in any communication model. It is one of the most crucial parts of an electrical circuit. Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication Objective: Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication. Methods: In order to make the PWM suitable for GC, we have implemented the design on VIVADO ISE from Xilinx. The power analysis as well as resource utilization are targeted on three different FPGAs. Results: Different IO standards of Stub Series Terminated Logic (SSTL) family are explored at different FPGA’s. Power analysis is deployed on the 7 series FPGAs of 3 different categories i.e., Spartan 7 (channel length = 28 nm), Kintex 7 (channel length = 20 nm) and ultra scale Zynq 7 (channel length = 16 nm). Conclusion: It can be concluded from power analysis that SPARTAN-7 device is the most powerefficient and ZYNQ Ultra scale+utilizes the highest amount of power. However, KINTEX-7 Ultrascale device lies in the middle of both these devices as far as power consumption is concerned. There is a reduction of 43.07% TP consumption for SPARTAN-7 device with SSTL135 IO when equated with ZYNQ Ultra scale+ with SSTL18_I IO. Also, it can be observed from sections 5.1, 5.2 and 5.3 that there is more contribution of DP in TP consumption than SP. Hence the device utilizes additional power when it is in active state than static state. Since PWM generator is an integral part of data and wireless communication, it should require less power for proficient transmission and wellorganized green computing and communication.

RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA

Finite field multiplication is a non-linear transformation operator that appears in the majority of symmetric cryptographic algorithms. Numerous specified finite field multiplication units have been proposed as a fundamental module in the coarse-grained reconfigurable cipher logic array to support more cryptographic algorithms; however, it will introduce low flexibility and high overhead, resulting in reduced performance of the coarse-grained reconfigurable cipher logic array. In this article, a high-flexibility and low-cost reconfigurable Galois field multiplication unit (RGMU) is proposed to balance the tradeoffs between the function, delay, and area. All the finite field multiplication operations, including maximum distance separable matrix multiplication, parallel update of Fibonacci linear feedback shift register, parallel update of Galois linear feedback shift register, and composite field multiplication, are analyzed and two basic operation components are abstracted. Further, a reconfigurable finite field multiplication computational model is established to demonstrate the efficacy of reconfigurable units and guide the design of RGMU with high performance. Finally, the overall architecture of RGMU and two multiplication circuits are introduced. Experimental results show that the RGMU can not only reduce the hardware overhead and power consumption but also has the unique advantage of satisfying all the finite field multiplication operations in symmetric cryptography algorithms.

An field programmable gate array (FPGA)-based device for charge-state readout of nitrogen-vacancy (NV) center in diamond with nanosecond feedback speed

Ionization of nitrogen-vacancy (NV) center in diamond from the NV− to NV0 state is a destructive process in applications, where a large amount of time is cost for high-fidelity readout. To this end, real-time adaptive feedback would be helpful to improve the readout efficiency. Here, we develop a field programmable gate array-based device that supports complex calculation and real-time feedback at the nanosecond level. This device integrates a time tagger for photon input, a programmable logic arrays for real-time calculation, and a 20-channel pulse streamer for control output. Based on this device, we demonstrate a high-efficiency of real-time charge-state readout. With this device, the signal-to-noise ratio of maximal adaptive-decision-based charge-state readout can be significantly reduced. Moreover, we demonstrate an application of NV− purification with the real-time feedback, where the contrast of spin-state-dependent fluorescence is improved from 31.7% to 35.0%. The device can be easily extended to other quantum systems.

Reconfigurable stateful logic design in the one-transistor-one-memristor crossbar array for logic-in-memory computing

A reconfigurable stateful logic circuit based on one-transistor-one-memristor (1T1M) crossbar array is proposed by combining the advantages of stateful logic and 1T1M array. Boolean logic operations can be realized not only on the row but also on the column of 1T1M array, which improves the flexibility and computing capability of the array. The same logic circuit can be reconfigured to perform different Boolean logic operations. Then, based on the parallelism of the array and the proposed stateful logic, the 2-bit multiplier and the encryption and decryption circuit of binary images are designed, reducing the logic operating steps. Finally, the circuit simulations of the proposed row-wise logic, the column-wise logic, the 2-bit multiplier as well as the encryption and decryption of SWU binary images are carried out in the 1T1M array. In the proposed stateful logic, the storage of logic inputs, the logic operation process, and the storage of operation results are all executed in 1T1M array, which integrates storage and computation, and effectively overcomes the sneak path problem. The entire scheme provides the application potential of memristor based on two-dimensional materials or conventional materials, opening up a new approach for the next-generation computing.

Test Method of Secure and Controllable FPGA Chip Used in Flexible DC Transmission Control and Protection System

Flexible DC transmission control and protection system is a high-performance distributed computing system, which has the characteristics of high-speed data acquisition and fast processing, and uses a large number of high-performance FPGA (Field Programmable Logic Array) chips. FPGA has the characteristics of high integration and complex manufacturing process, and its security and controllability is faced with many challenges. The reliability of FPGA is an important standard to measure its performance, so reliability test fault screening is very important to ensure its normal operation. Although the automatic test equipment (ATE) can test the fault of FPGA, it is not convenient for field testing due to the price, test environment and other factors. In this paper, a design scheme of built-in self-test (BIST) for fault detection and fault diagnosis is proposed, which can detect faults of look-up table (LUT) and interconnection resources (wires and programmable switches). At the same time, considering the effect of rising temperature on fault probability, a controlled self-heating element (SHE) is constructed by using the internal resources of FPGA to provide the required temperature for BIST testing. Finally, an integrated layout scheme of BIST and SHE is proposed. An experiment of self-heating of FPGA chip is completed by TSINGHUA PGL22G, which verifies the correctness and feasibility of the theory.

On algebraic array theories

Automatic verification of programs manipulating arrays relies on specialised decision procedures. A methodology to classify the theories handled by these procedures is introduced. It is based on decomposition theorems in the style of Feferman and Vaught. The method is applied to obtain an extension of combinatory array logic that is closed under propositional operations and Hoare triples. A classification according to expressiveness of six different fragments studied in the literature is given.

Efficient Large-Scale Virtual Screening Based on Heterogeneous Many-Core Supercomputing System.

With the rapid growth of virtual drug data- bases, the need for efficient molecular docking tools for large-scale screening is also growing. We have developed Vina@QNLM 2.0, a novel molecular docking system that leverages the logical processing units and computational processing arrays of heterogeneous multicore architecture processors. Compared to Vina@QNLM, the new version optimizes the docking speed without sacrificing accuracy. This greatly improves the scoring capability for large molecules (molecular weight > 500). Simultaneously, the new system provides enhanced support for applications such as reverse target finding through an improved parallel strategy. Vina@QNLM 2.0 achieves a speedup 20 times higher than that, using logical processing units only during a single docking process. Additionally, we successfully scaled the reverse target finding a task to 122,401 kernel groups with a robust scalability of 80.01%. In practice, we completed a reverse target-seeking for nine glycan molecules with 10,094 proteins within 1 hour.

Design of Multi-circuit Motor Control System based on Fabric Defect Detection Device

In order to realize the motion control of multiple motors of the fabric defect detection device, a ZYNQ-based multiple motor control system is designed in conjunction with the fabric defect detection device. In this system, pulse width modulation technique is used to control the multi-channel motors. The flexible logic operability of FPGA is utilized to achieve real-time high-speed control of multi-channel pins, where FPGA is responsible for data caching and acquisition control, and ARM is responsible for data communication and transmission. The logic array was programmed and simulated in Vivado software. Simulation results show that the system is able to control multiple motors synchronously and stably, verifying the effectiveness and feasibility of the system.

Performing photonic nonlinear computations by linear operations in a high-dimensional space

Abstract As photonic linear computations are diverse and easy to realize while photonic nonlinear computations are relatively limited and difficult, we propose a novel way to perform photonic nonlinear computations by linear operations in a high-dimensional space, which can achieve many nonlinear functions different from existing optical methods. As a practical application, the arbitrary binary nonlinear computations between two Boolean signals are demonstrated to implement a programmable logic array. In the experiment, by programming the high-dimensional photonic matrix multiplier, we execute fourteen different logic operations with only one fixed nonlinear operation. Then the combined logic functions of half-adder and comparator are demonstrated at 10 Gbit/s. Compared with current methods, the proposed scheme simplifies the devices and the nonlinear operations for programmable logic computing. More importantly, nonlinear realization assisted by space transformation offers a new solution for optical digital computing and enriches the diversity of photonic nonlinear computing.

RECURSIVE TERNARY-BASED ALGORITHM FOR COMPUTING PRIME IMPLICANTS OF MULTI-OUTPUT BOOLEAN FUNCTIONS

The problem of computing the set of prime implicants to represent a Boolean function is a classical problem that is still considered a running problem for research because all known approaches have limitations. The article reviews existing methods for computing prime implicants and highlights their limitations, particularly for multi-output functions and limited scalability due to the growth in memory required to complete the computation. Then it proposes a recursive ternary-based minimization algorithm to compute the prime implicants of multi-output Boolean functions. The algorithm is based on the concept of Programmable Logic Array (PLA) tables, which provide a structured and efficient representation of Boolean functions. The algorithm takes advantage of the ternary logic system to efficiently compute the prime implicants while maintaining scalability for large and complex functions, which has significant implications for digital circuit design and optimization.

Parallel Finite Field Algorithms for Communications and Sensor Networks

Sensor network integrates sensor technology, embedded computing technology, modern network and wireless communication technology, distributed information processing technology, etc. It can monitor, perceive and collect the information of various environments or monitoring objects in real time through various integrated micro sensors, and process the information through the embedded system. The perceived information is transmitted to the user terminal by multi-hop relay through the random ad-hoc wireless communication network. The coding of communications and sensor networks affects the efficiency of communication. The main coding technology is based on finite field. Among operations in finite fields, divisions are time-consuming operations since they are generally computed via inversions and multiplications. We present techniques to exploit extend binary trees for fast divisions in finite fields. We implement the finite field algorithm on Field Programmable Logic Arrays (FPGAs) in a parallel way. The implementation result from FPGAs shows that the parallel finite field algorithm can speed up the process of coding of communications and sensor networks.

Development of multichannel readout electronics prototype system for TPC detector of CSR External-Target Experiment

We present a multichannel readout electronics prototype system developed for the Time Projection Chamber (TPC) detector of CSR External-Target Experiment (CEE). The whole system consists of two Front-End readout Electronics (FEE) boards, fiber converters, host computers and a trigger fan-out board. A single FEE board is mainly equipped with four SAMPA chips and a Field Programmable Logic Array (FPGA), processing 128 channels of signals from the TPC detector. The SAMPA chips convert the charge signals into digital signals and send them to FPGA for data processing, and then transmit the data to the host computer through a fiber converter. The control commands from the host computer software realize the control of SAMPA and monitor temperature and current. In the dynamic range of input charge from 2 fC to 100 fC, the readout electronics output amplitude linearity is better than 1%. The relative energy resolution of electronics is about 23% at a minimum input charge of 1.4 fC. The test results with TPC illustrate that with a 55Fe source, an energy resolution of 28.5% was acquired, and with cosmic rays, the track resolution on the pad plane is less than 390μm.

PID-FUZZY Control System for Autonomous Underwater Vehicles (AUV): Highly Accurate FPGA Implementation

Because of the linear and nonlinear variations in the operating environment, autonomous underwater vehicles (AUVs) are one of the most difficult applications. The complexity of the control algorithm should be less for real-time implementation in a field programable gate array logic (FPGA) device. In this work, a highly accurate FPGA implementation of PID-Fuzzy control strategy is proposed for an AUV operation that is extremely precise. Parameters such as weight, water density, and depth are used to perform highly efficient and accurate control for the proposed system. A type II fuzzy logic controller and accompanying proportional-integral- derivative controller are used to confine pitch and depth boundaries. The proposed design is modeled using SIMULINK software, and Verilog code is generated using hardware description language coder from MATLAB. Xilinx software is used to synthesize the Verilog code for spartan FPGA. The proposed technique improves the accuracy and reduces the response time when compared to the conventional control strategy.

A comparison of an evolvable hardware controller with an artificial neural network used for evolving the gait of a hexapod robot

This paper investigates the implementation of a novel evolvable hardware controller used in evolutionary robotics. The evolvable hardware consists of a Cartesian based array of logic blocks comprised of multiplexers and logic elements. The logic blocks are configured by a bit stream which is evolved using a genetic algorithm. A comparison is performed between an evolvable hardware and an artificial neural network controller evolved using the same genetic algorithm to produce the gait of a hexapod robot. To compare the two controllers, differences in their evolutionary efficiency and robot performance are investigated. The evolutionary efficiency is measured by the required number of generations to achieve an optimal fitness. An optimal hexapod controller allows the robot to walk forward in a straight line maintaining a constant heading and body attitude. It was found that the evolutionary efficiency and performance of the evolvable hardware and artificial neural network were similar, however the EHW was the most evolutionary efficient requiring less generations on average to evolve. Both evolved controllers were evaluated in simulation, and on a physical robot using a softcore processor and custom hardware implemented on a FPGA. The implementation showed that the controllers performed equally well when deployed, allowing the hexapod to meet the optimal gait criteria. These findings have shown that the evolvable hardware controller is a valid option for robotic control of a multilegged robot such as a hexapod as its evolutionary efficiency and deployed performance on a real robot is comparable to that of an artificial neural network. One future application of these evolvable controllers is in fault tolerance where the robot can dynamically adapt to a fault by evolving the controller to adjust to the fault conditions.

Embeddable parallel digital image of doubly-fed induction generator

Due to the complexity of the structure of doubly-fed induction generator (DFIG), it is difficult to conduct real-time simulation. For this reason, this paper designs an embeddable parallel digital image IP of DFIG based on field programmable logic array (FPGA) to realize efficient electromagnetic simulation of DFIG. First, this paper proposes a virtual capacitor equivalent method for induction machine equivalent “T” circuit decoupling; Secondly, based on the principle of data independence and parallelism within the time step, a parallel algorithm for the internal components of DFIG is proposed; Finally, the FPGA-DFIG digital image constructed in this paper is connected to the RT-LAB/power grid, and hardware experiments are carried out under three working conditions: steady state, voltage sag and DC side fault. The experimental results are compared with the simulation results of DFIG grid connected system built in MATLAB/Simulink environment to verify the effectiveness and rapidity of the methods and models proposed in this paper.

An eFPGA Generation Suite with Customizable Architecture and IDE

From edge devices to cloud servers, providing optimized hardware acceleration for specific applications has become a key approach to improve the efficiency of computer systems. Traditionally, many systems employ commercial field-programmable gate arrays (FPGAs) to implement dedicated hardware accelerator as the CPU's co-processor. However, commercial FPGAs are designed in generic architectures and are provided in the form of discrete chips, which makes it difficult to meet increasingly diversified market needs, such as balancing reconfigurable hardware resources for a specific application, or to be integrated into a customer's system-on-a-chip (SoC) in the form of embedded FPGA (eFPGA). In this paper, we propose an eFPGA generation suite with customizable architecture and integrated development environment (IDE), which covers the entire eFPGA design generation, testing, and utilization stages. For the eFPGA design generation, our intellectual property (IP) generation flow can explore the optimal logic cell, routing, and array structures for given target applications. For the testability, we employ a previously proposed shipping test method that is 100% accurate at detecting all stuck-at faults in the entire FPGA-IP. In addition, we propose a user-friendly and customizable Web-based IDE framework for the generated eFPGA based on the NODE-RED development framework. In the case study, we show an eFPGA architecture exploration example for a differential privacy encryption application using the proposed suite. Then we show the implementation and evaluation of the eFPGA prototype with a 55nm test element group chip design.

Identifying Indoor Objects Using Neutrosophic Reasoning for Mobility Assisting Visually Impaired People

Indoor object detection is a fundamental activity for the development of applications of mobility-assistive technology for visually impaired people (VIP). The challenge of seeing interior objects in a real indoor environment is a challenging one since there are numerous complicated issues that need to be taken into consideration, such as the complexity of the background, occlusions, and viewpoint shifts. Electronic travel aids that are composed of the necessary sensors may assist VIPs with their navigation. The sensors have the ability to detect any obstacles, regardless of whether they are static or dynamic, and offer information on the context of an interior scene. The characteristics of an interior scene are not very clear and are subject to a great deal of variation. Recent years have seen the emergence of methods for dealing with issues of this kind, some of which include the use of neural networks, probabilistic methods, and fuzzy logic. This study describes a method for detecting indoor objects using a rotational ultrasonic array and neutrosophic logic. A neutrosophic set has been seen as the next evolution of the fuzzy set because of its indeterminate membership value, which is absent from conventional fuzzy sets. The suggested method is constructed to reflect the position of the walls (obstacle distance) and to direct the VIP to move freely (ahead, to the right, or to the left) depending on the degree of truthiness, the degree of indeterminacy, and the degree of falsity for the reflected distance. The results of the experiments show that the suggested indoor object detecting system has good performance, as its accuracy rate (a mean average precision) is 97.2 ± 1%.

Latest Advances on Security Architecture for 5GTechnology and Services

The roll out of the deployment of the 5G technology has been ongoing globally. The deployment of the technologies associated with 5G has seen mixed reaction as regards its prospects to improve communication services in all spares of life amid its security concerns. The security concerns of 5G network lies in its architecture and other technologies that optimize the performance of its architecture. There are many fractions of 5G security architecture in the literature, a holistic security architectural structure will go a long way in tackling the security challenges. In this paper, the review of the security challenges of the 5G technology based on its architecture is presented along with their proposed solutions. This review was carried out with some keywords relating to 5G securities and architecture; this was used to retrieve appropriate literature for fitness of purpose. The 5G security architectures are majorly centered around the seven network security layers; thereby making each of the layers a source of security concern on the 5G network. Many of the 5G security challenges are related to authentication and authorization such as denial-of-service attacks, man in the middle attack and eavesdropping. Different methods both hardware (Unmanned Aerial Vehicles, field programmable logic arrays) and software (Artificial intelligence, Machine learning, Blockchain, Statistical Process Control) has been proposed for mitigating the threats. Other technologies applicable to 5G security concerns includes: Multi-radio access technology, smart-grid network and light fidelity. The implementation of these solutions should be reviewed on a timely basis because of the dynamic nature of threats which will greatly reduce the occurrence of security attacks on the 5G network.

Monolithic Tandem Vertical Electrochemical Transistors for Printed Multi-Valued Logic.

Organic electrochemical transistors (OECTs) have recently emerged as a feasible candidate to realize the next generation of printable electronics. Especially, their chemical versatility and the unique redox-based operating principle have provided new possibilities in high-functioning logic circuitry beyond the traditional binary Boolean logic. Here, a simple strategy to electrochemically realize monolithic multi-valued logic transistors is presented, which is one of the most promising branches of transistor technology in the forthcoming era of hyper Moore's law. A vertically stacked heterogeneous dual-channel architecture is introduced with a patterned reference electrode, which enables a facile manifestation of stable and equiprobable ternary logic states with a reduced transistor footprint. The dual-ion-penetration mechanism coupled with ultrashort vertical channel even allows a very-high accessing frequency to multiple logic states reaching over 10MHz. Furthermore, printed arrays of ternary logic gates with full voltage swing within 1V are demonstrated.