Logic Area Research Articles

Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process

Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process

Memory Requirement Reduction Method for Successive Cancellation Decoding of Polar Codes

The invention of Polar codes by Arikan is a major breakthrough in coding theory. Polar Code decoding algorithm implementation is a major challenge to recover transmitted information. Thus, several polar decoder architectures were proposed in the literature. All of these architectures focused on reducing the computational hardware complexity and increasing the throughput of polar decoders. However, the memory requirements remain a limiting implementation factor that has not been fully adressed yet. This paper proposes a novel method to simply redesign existing decoder architectures in order to use less memory at the cost of some extra computational logic. The main idea is to replace memory sections — assigned to store intermediate results — with computational logic. The method, applied to an existing decoder $\mathcal {D}$ , results in what is called a mixed decoder architecture based on $\mathcal {D}$ , denoted $M({\mathcal {D}})$ . Since previous decoders are based on the semi-parallel decoder architecture, we first apply the memory requirement reduction technique to a semi-parallel decoder. Analyses, together with logic synthesis results, show that the gains brought by the reduction in memory area requirements are well worth the induced extra computational logic area. We show that the memory requirement reduction technique can increase the speed/area ratio by 25 % when implemented in standard cell technology (ST 65 nm). We also provide some insights on the potential gain that this method would provide on state-of-the-art decoders implemented on FPGA devices. For example, it is shown that the proposed method can lower the decoder memory requirements by 50 % while using less than 20 % of the FPGA logic elements, and implying a latency penalty of less than 5 %.

Hybrid LUT/Multiplexer FPGA Logic Architectures

Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Multiple hybrid configurable logic block architectures, both nonfracturable and fracturable with varying MUX:LUT logic element ratios are evaluated across two benchmark suites (VTR and CHStone) using a custom tool flow consisting of LegUp-HLS, Odin-II front-end synthesis, ABC logic synthesis and technology mapping, and VPR for packing, placement, routing, and architecture exploration. Technology mapping optimizations that target the proposed architectures are also implemented within ABC. Experimentally, we show that for nonfracturable architectures, without any mapper optimizations, we naturally save up to ~8% area postplace and route; both accounting for complex logic block and routing area while maintaining mapping depth. With architecture-aware technology mapper optimizations in ABC, additional area is saved, post-place-and-route. For fracturable architectures, experiments show that only marginal gains are seen after place-and-route up to ~2%. For both nonfracturable and fracturable architectures, we see minimal impact on timing performance for the architectures with best area-efficiency.

PMGA and its application in area and power optimization for ternary FPRM circuit**Project supported by the Natural Science Foundation of Zhejiang Province (No. LY13F040003), the National Natural Science Foundation of China (Nos. 61234002, 61306041), and the K. C. Wong Magna Fund in Ningbo University.

Based on the research of population migration algorithms (PMAs), a population migration genetic algorithm (PMGA) is proposed, combining a PMA with a genetic algorithm. A scheme of area and power optimization for a ternary FPRM circuit is proposed by using the PMGA. Firstly, according to the ternary FPRM logic function expression, area and power estimation models are established. Secondly, the PMGA is used to search for the best area and power polarity. Finally, 10 MCNC Benchmark circuits are used to verify the effectiveness of the proposed method. The results show that the ternary FPRM circuits optimized by the PMGA saved 13.33% area and 20.00% power on average than the corresponding FPRM circuits optimized by a whole annealing genetic algorithm.

Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA

The authors explore and design the traditional field-programmable gate array (FPGA) interconnect topologies and architectures that can play an important role in improving performance and density. The main architectures under exploration are tree-based and island-style Manhattan Mesh. Mesh-based design is the most common industrial and academic architecture. Numerous research and industrial designs have been developed to improve mesh-based FPGAs' performance, area, and power consumption. Nonetheless, when looking at performance metrics such as speed, area, and power, the gap is generally very wide for FPGAs compared to application-specific integrated circuits (ASICs). Despite their good properties, such as high logic density and area advantage, tree-based architectures have been overlooked up to now. This article addresses long wire length issues associated with tree-based programmable interconnects using 3D design and manufacturing technologies. Using their dedicated 3D design and optimization methodology, the authors show that 3D tree-based architecture is 1.5 times faster than the mesh-based counterpart.

Combined Partitioning Hardware-Software Algorithms

In recent years, meta-heuristics have become increasingly interesting in solving combinatorial problems including hardware-software partitioning. In this paper, we present a comparative study between some algorithms which involve meta-heuristics based on Tabu search, genetic algorithm and Binary Search Trees to address the problem of hardwaresoftware partitioning. In fact, meta-heuristics can produce acceptable solutions within a reasonable time, but they do not guarantee an optimal solution. We have proposed these algorithms to find the efficient hardware-software partition that minimizes the logic area of System on a Programmable Chip while respecting a time constraint. This paper presents an analysis of these meta-heuristics by identifying the fundamental ideas guiding the choice of a meta-heuristic in practice.

A scalable architecture for geometric correction of multi-projector display systems

Multi-projector displays allow the realization of large and immersive projection environments by allowing the tiling of projections from multiple projectors. Such tiled displays require real time geometrical warping of the content that is being projected from each projector. This geometrical warping is a computationally intensive operation and is typically applied using high-end graphics processing units (GPUs) that are able to process a defined number of projector channels. Furthermore, this limits the applicability of such multi-projector display systems only to the content that is being generated using desktop based systems. In this paper we propose a platform independent FPGA based scalable hardware architecture for geometric correction of projected content that allows addition of each projector channel at a fractional increase in logic area. The proposed scheme provides real time correction of HD quality video streams and thus enables the use of this technology for embedded and standalone devices.

효율적인 필터 계수 추출을 위한 HEVC 부호화기의 고성능 ALF 하드웨어 설계

This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz. 키워드 : HEVC encoder, ALF(적응적 루프 필터), 촐레스키 분해, FPGA Key word : HEVC encoder, ALF(Adaptive Loop Filter), Cholesky decomposition, FPGA

English

In many highway traffic accidents, the main cause is straight line detection. So as to avoid accidents straight line detection is an important component of intelligent transportation systems. This paper describes different lane marking algorithms and analyses advantages and disadvantages of lane detection algorithms. This paper illustrates the survey of B-Snake algorithm, RANSAC algorithm for urban streets, unsupervised and adaptive classifier technique, robust and lane detection algorithm in challenging scenarios .The most effective technique for straight line detection with reduced logic area and memory utilization is hough transform. The comparative study shows that hough transform based lane detection algorithm is very reliable.

A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps

Prior work has shown that due to the overhead incurred in enabling reconfigurability, field-programmable gate arrays (FPGAs) require 21× more silicon area, 3× larger delay, and 10× more dynamic power consumption compared with application-specific integrated circuits (ASICs). We have earlier presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE). It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density by an order of magnitude. Since logic folding reduces area usage significantly, on-chip communications tend to become localized. To take full advantage of this fact, we propose a new architecture, called fine-grain dynamically reconfigurable (FDR), that consists of an array of homogeneous reconfigurable logic elements (LEs). Each LE can be arbitrarily configured into a lookup table (LUT) or interconnect or a combination of both. This significantly enhances the flexibility of allocating hardware resources between LUTs and interconnects based on application needs. The proposed FDR architecture eliminates most of the long-distance and global wires, which occupy most of the area in conventional FPGAs. Fine-grain dynamic reconfiguration is enabled by local embedded static RAM blocks. The experiments show that, on an average, area, delay, and power are improved by 9.14×, 1.11×, and 1.45×, compared with a conventional FPGA architecture that does not use the concept of logic folding. Compared with NATURE with deep logic folding, area, delay, and power are improved by 2.12×, 3.28×, and 1.74×, respectively. Although this does not eliminate the FPGA-ASIC area/delay/power gaps, it makes progress toward bridging these gaps.

Methodology and Application of the Detection of Invisible Defect by Voltage Contrast Inspection

The study aimed at the detection of non-visual defects of poly gate CT leakage at dense logic area by voltage-contrast (VC) inspection. At the same time, some new steps after N-type plus (NP) source drain (S/D) implantation of front-end-of-the-line (FEOL) was proposed and compared to detect poly gate CT leakage at the dense logic area. The cause of t`he poly gate CT leakage was the extreme tiny poly footing which was too small to be detected by the optical system. The PG leakage was obviously impacted by poly etch process and the step height between active area (AA) and shallow trench isolation (STI). The poly gate CT leakage defects were solved by inline controlling to reduce the step height between AA and STI and optimizing poly etch process. Furthermore, the application extended the VC inspection from just middle-end-of-the-line to FEOL of semiconductor technology.

Las tecnologías inteligentes y el aprendizaje

The man seen as the most developed of all living species and the only one who can think rationally, plan and design strategies to create and innovate, the brain has to be one of the most functional systems and organized when it “knows” about of Systems Theory, as well as being highly “complex”, which in his limited understanding and comprehension. Since the introduction by 1940 of Informatics, technologies, both soft and hard , apply in various activities related to human behavior, it is so Artificial Intelligence, Genetic Algorithms, Fuzzy Logic, Neuromarketing and other area of knowledge, made great and constant efforts to study the structure and behavior of the human brain within the many activities of the brain, is to store longterm or short-term information and to be able to recover, this engaging Cognitive Sciences. The research, this is in progress and it investigates methodologies and didactic to active level can compromise the design and development of a learning environment to support learning of Accounting Fundamentals, Student Body, but doing a bet to find another dynamic, proposes to venture into the Neuromarketing, area brand new knowledge, which has conducted research with important results regarding motivation, fixation and recall of brands and/or products for later consumption; retaking these achievements by Neuromarketing proposed to include some to influence student learning, as a brand new item and to consider in the design and construction of the learning environment.

Minimizing Design Costs of an FIR Filter Using a Novel Coefficient Optimization Algorithm

This work presents a novel coefficient optimization algorithm to reduce the area and improve the performance of finite impulse response (FIR) filter designs. Two basic architectures are commonly used in filters—direct and transposed. The coefficients of a filter can be encoded in the fewest possible nonzero bits using canonic signed digit (CSD) expressions. The proposed optimization algorithm can share common subexpressions (CS) and reduce the number of replicate operations that involve the CSD coefficients of filters with a transposed architecture. The effectiveness of the algorithm is confirmed by using filters with the collision detection multiple access (CDMA) standard, the 121-tap high-pass band, and 105- and 325-tap low-pass bands as benchmarks. For example, the proposed algorithm used in the optimization of 105-tap filter has a 30.44% smaller combinational logic area and a 16.69% better throughput/area than those of the best design that has been developed to date. Experimental results reveal that the proposed algorithm outperforms earlier designs.

True hardware random number generation implemented in the 32-nm SOI POWER7+ processor

This paper provides a description of the hardware random number generator that is implemented on the IBM POWER7+™ processor. We discuss the underlying mechanism using basic ring oscillator circuits implemented in standard digital logic circuits. The source of entropy is based on sampling phase jitter in the ring oscillators, and the rate of phase jitter accumulation is measured. We show that the design is simple and robust yet able to generate a high rate of random bits while using a minimum of logic area. The design is very resistant to physical manipulation, being able to produce solid entropy values under environmental conditions that exceed the requirements of the surrounding circuitry. With a design-specific mechanism to correct for ring oscillator sample bias, the output shows a very high rate of entropy, which is validated.

Nanomagnetic Logic Microprocessor: Hierarchical Power Model

The interest in emerging nanotechnologies has been recently focused on nanomagnetic logic (NML), which has unique appealing features. NML circuits have very low power consumption and, because of their magnetic nature, maintain the information safely stored even without power supply. The nature of these circuits is much different from that of CMOS circuits. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics; and 3) modeling performance aspects such as speed and power, together with logic behavior. In this paper, we present a very-high-speed integrated circuits HDL (VHDL) behavioral model for NML circuits, which allows the evaluation of not only the logic behavior but also its power dissipation. It is based on a technological solution called “snake-clock.” We demonstrate this model using a case study which offers the right variety of internal substructures to test the method: a 4-bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area, and power dissipation, which we evaluate using a benchmark division algorithm. The results highlight the flexibility and the efficiency of this model, as well as the remarkable improvements that it brings to the analysis of NML circuits.

Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint

Satisfying the timing constraint is the utmost concern in the integrated circuit design and it is true that most critical timing paths in a circuit cover one or more arithmetic components such as adder, subtractor, and multiplier of which addition logic is commonly involved. This work addresses the problem of redesigning the addition logic (in a form of hybrid adder) on a critical timing path to meet the timing constraint while minimally allocating the required addition logic. Unlike the conventional hybrid adder design schemes in which they assume uniform or specific patterns of input signal arrival times and minimize the latest timing of the output signals, our work extracts the required timing of each output signal as well as the input arrival times directly from the circuit and resynthesizes the addition logic by creating a customized hybrid adder that is best suited, in terms of logic area, for meeting the timing constraint of the circuit. Specifically, we propose a systematic approach of hybrid adder design exploration, basically following the principle of dynamic programming with well-controlled pruning techniques. This work is realistic and practically very useful in that it can be used as a timing optimizer to the computation-intensive circuits with a tight timing budget. We provide a set of diverse experimental data to show how much the proposed hybrid adder scheme is effective in meeting or reducing timing while maintaining the circuit area as minimal as possible.

Performance Evaluation of Hybrid Reconfigurable Computing Architecture over Symmetrical FPGA

For last few decades, reconfigurable devices have been extensively used in digital systems. Reconfigurable computing using FPGA devices provide a method to utilize the available logic resources on the chip for various computations. The basic ability of reconfigurable computing is to perform computations in hardware to increase performance, while retaining the flexibility of application software. The two main types of programmable logic devices, field-programmable gate arrays (FPGA) based on LUTs technology and complex programmable logic device (CPLD) based on PLAs technology. They are both widely used and each contributing particular strengths in the area of reconfigurable system design. We identified Hybrid LUTs/PLAs architectures as Hybrid Reconfigurable Computing Architectures (HRCA). The purpose of this paper is to evaluate the performance of HRCA over regular FPGA device for reconfigurable computing by mixing of Look up tables (LUTs) and Programmable logic arrays (PLAs) architecture. The basis of the HRCA is that some parts of digital circuits are well-suited for execution with LUTs, but other parts help more from the PLAs structures. For several classes of high performance applications, HRCA offers significant savings in total computational delay comparison with a symmetrical FPGA which contain only LUTs. It also offers some improvements in logical area and power consumption. Experimental results based on MCNC benchmark circuit were performed on implemented HRCA CAD and compare between HRCA and symmetrical FPGA. Initially results indicate that noteworthy saving in computational delay and logic area of HRCA over symmetrical FPGA.

Optimizing Functional Unit Binding During High-Level Synthesis

One of the three central synthesis tasks in a typical high-level synthesis system is binding which assigns operations to functional units, values to storage units, and interconnects these components with wires and buses to form a complete data path. The data path constitutes a considerable area of an application specific integrated circuit (ASIC) or field-programmable gate array (FPGA). This article proposes a solution that incorporates a simulated annealing approach after binding operations to functional units in the goal of reducing overall area. When standard scheduling techniques are used, this solution assigns operations to the same hardware resource when those operations’ inputs or outputs are bound to the same storage units. The optimization procedure swaps possible nodes to decrease the number of needed multiplexers in the final design. In typical benchmarks, the savings obtained in terms of multiplexer area reach 33.6% with an average of 17.1%; moreover, the overall logic area savings reach 18.2% with an average of 6.6%.

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

Because of numerous circuit resources of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a small-memory logic cell, COGRE, to reduce the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPN-equivalence class. The results of our investigation show that only small portions of the NPN-equivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPN-equivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this analysis, we develop COGRE architectures composed of several NAND gates and programmable inverters. The experimental results show that the logic area of 4-COGRE is smaller than that of 4-LUT and 5-LUT by approximately 35.79% and 54.70%, respectively. The logic area of 8-COGRE is 75.19% less than that of 8-LUT. Further, the total number of configuration memory bits of 4-COGRE is 8.26% less than the number of configuration memory bits of 4-LUT. The total number of configuration memory bits of 8-COGRE is 68.27% less than the number of configuration memory bits of 8-LUT.

Supply chain networks and service‐dominant logic: suggestions for future research

PurposeThe service‐dominant (S‐D) logic views supply chains as value co‐creation networks. These networks promote knowledge growth amongst network members via resource deployment and coordination. The exchange of knowledge and utilization of operant resources among the network members leads to co‐created service offerings and value proposals for the end‐users, with the ultimate goal of transforming end‐user experiences to perceptions of superior value‐in‐use. The purpose of this paper is to develop an illustration of the value co‐creation concept and use this illustration as guide to examine the research gaps that are yet to be tapped in the area where supply chain networks and S‐D logic intersects.Design/methodology/approachThe literature on S‐D logic is reviewed and research gaps are identified and categorized in three specific groups.FindingsThree categories of research gaps in S‐D logic and supply chain management (SCM) areas include: gaps in utilization of internal operant resources by suppliers, manufacturers, and intermediaries; gaps in knowledge exchange and operant resource utilization between suppliers, manufacturers, and intermediaries; and gaps in knowledge exchange and operant resource utilization between end‐users and value co‐creation network partners.Originality/valueAn illustration of the value co‐creation network from the supply chain perspective is presented in this paper. The illustration of the value co‐creation network provided the guidance to categorize various research gaps in the area of S‐D logic and SCM. This categorization offers a structure from which more systematic research may be produced. It is the authors' hope that the organization and guidance provided in the paper for specific research topics in the S‐D logic area can result in research streams that could potentially offer significant contributions to SCM theory development.