Methodology and Application of the Detection of Invisible Defect by Voltage Contrast Inspection

Abstract

The study aimed at the detection of non-visual defects of poly gate CT leakage at dense logic area by voltage-contrast (VC) inspection. At the same time, some new steps after N-type plus (NP) source drain (S/D) implantation of front-end-of-the-line (FEOL) was proposed and compared to detect poly gate CT leakage at the dense logic area. The cause of t`he poly gate CT leakage was the extreme tiny poly footing which was too small to be detected by the optical system. The PG leakage was obviously impacted by poly etch process and the step height between active area (AA) and shallow trench isolation (STI). The poly gate CT leakage defects were solved by inline controlling to reduce the step height between AA and STI and optimizing poly etch process. Furthermore, the application extended the VC inspection from just middle-end-of-the-line to FEOL of semiconductor technology.