Mechanism and detection of poly gate leakage with nonvisual defects by voltage contrast inspection

Abstract

The research aims at nonvisual defects causing the poly gate leakage failure and the corresponding inline voltage-contrast (VC) inspection. Electron beam inspection (EBI) begins to be frequently used for scanning either SRAM or DRAM cell area in nano-scaled technologies. The research, furthermore, extends EBI to logical area of an ASIC product and proposes an inline detectable methodology for gate leakages. Extreme tiny and nonvisual residues could happen during gate etch processes by the step height between active area (AA) and shallow trench isolation (STI), and the tiny defects are difficult to be located even some of those did lead to chip probe (CP) test failure. The subsequent implant processes would punch through those tiny poly residues, make the residue being conductive, and finally electrons on the gate would leak to the ground through the residue. Those nonvisual residues act as bridges for gate leakages. EBI with designed positive charging modes was applied into the series of implement steps and found the leakage by a significant voltage contrast signal post the source/drain implantation. The bright VC of the gate poly implied the leakage electrons charging on the gate. A series of process experiments based on the model for reducing leakages was tested and quickly verified by the EBI in front end of the line. An optimal process integration condition was soon carried out with a significant chip yield enhancement.