Logic Blocks Research Articles

FPGA Implementation of Image Ordering and Packing Algorithm for TuMag Camera

The TuMag instrument is a Tunable Magnetograph that has been designed to measure the magnetic field of the sun. This instrument and others will be connected to a telescope that will be sent into the stratosphere using a balloon for an uninterrupted observation of the sun for four days in the summer of 2022. The TuMag camera is a new development for implementing the image detector of the instrument. It is based on the GPIXEL GSENSE400-BSI scientific CMOS image sensor and an FPGA device in charge of controlling the image sensor, configuring it and grabbing images. FPGA device consists of an array of Configurable Logic Blocks. However, the sensor does not supply the image data in a row-by-column format. This task has to be done in the FPGA that controls the sensor because the frame grabber has a significant workload with the control of all the instruments, the telescope, the refrigeration, the navigation, and so on. This work describes the FPGA implementation of Image Ordering and Packing algorithm for TuMag Camera concerning the real-time ordering of the images before grabbing and sending to the Data Processing Unit.

Energy Efficient Configurable Layout of Logic Block in QCA Frame Work for an FPGA

Aims: Embedded system plays a vital role in today’s life. Hence, our interest is in areadelay- energy efficient embedded system design in post-CMOS technology, i.e., QCA. Objectives: The research is focused on efficient area-delay-energy Configurable Logic Block (CLB) design for Field-Programmable Gate Array architecture (FPGA) with successful simulation-based on next-generation technology, Quantum-dot cellular automata. Methods: Each proposed circuit is designed on post CMOS 4 dot 2 electron technology, i.e. QCA (Quantum dot Cellular Automata), is adopted in circuit implementation due to low power dissipation, high clock frequency and high package density. QCADesigner is used to verify the functionality of every circuit. QCAPro tool is used for determining power dissipation. Results: In contrast, a new approach of using de-multiplexer replacing the decoder has been introduced that results in the reduction of the average energy dissipation by almost 57%. A NOR based D flip-flop memory architecture and multiplexer are also used in the lookup table for the configurable logic block. The proposed architecture thus reduces the overall latency. The proposed CLB consists of 6356 QCA cells covering 7.44 um2 area. Write and read latency of proposed CLB are 12 and 7.25 QCA clock, respectively. Conclusion: The present paper concludes that read and write latency reduction occurs; average energy dissipation, leakage, and switching energy dissipation are reduced in a large amount resulting in an advantage of the overall minimization of the latency for the proposed CLB in the process.

A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection

The echo state network (ESN) is a recently developed machine-learning paradigm whose processing capabilities rely on the dynamical behavior of recurrent neural networks. Its performance outperforms traditional recurrent neural networks in nonlinear system identification and temporal information processing applications. We design and implement a cost-efficient ESN architecture on field-programmable gate array (FPGA) that explores the full capacity of digital signal processor blocks on low-cost and low-power FPGA hardware. Specifically, our scalable ESN architecture on FPGA exploits Xilinx DSP48E1 units to cut down the need of configurable logic blocks. The proposed architecture includes a linear combination processor with negligible deployment of configurable logic blocks and a high-accuracy nonlinear function approximator. Our work is verified with the prediction task on the classical NARMA dataset and a symbol detection task for orthogonal frequency division multiplexing systems using a wireless communication testbed built on a software-defined radio platform. Experiments and performance measurement show that the new ESN architecture is capable of processing real-world data efficiently for low-cost and low-power applications.

FEATURES OF USE OF LOGICAL BLOCKS OF DENNESH IN THE INTELLECTUAL DEVELOPMENT OF PRESCHOOL CHILDREN

The article identifies the relevance of the study of the problem of intellectual development of preschool children by didactic means. It is necessary to conduct research to find effective teaching aids that promote the intellectual development of preschool children. The definition of the concept of "intelligence", theoretical studies of intellectual development and intellectual education of preschoolers are presented. To substantiate the expediency of using and having a wide range of developmental possibilities of Dienes' logical blocks for the intellectual development of preschool children. Emphasis is placed on the fact that in the process of various actions with logical blocks, children master different skills, as well as develop logical and mathematical abilities and intelligence. The composition of a set of Dienes logic blocks is described. Some methodological aspects of working with them are described. The problem considered in the article has all prospects for further research. It is necessary to develop methodological recommendations for the use of logic games using Dienes blocks for the intellectual development of preschool children. The set of blocks attracts preschool children with a variety of shapes, bright colors, versatility in use. The varieties of games and game exercises with Dienes logic blocks are listed. We see the continuation of this study in the use of Dienes' logical blocks in the independent activities of preschool children. Examples of games and game exercises with Dienes logic blocks are given.

Noise investigation in a spin-based four-qubit GaAs block of self-assembled quantum dots

Optically controlled self-assembled quantum dots have received substantial attention in the quantum computing area, as techniques for initializing, manipulating, and reading out single spin qubits have been demonstrated in essence. The electron-spin coherence and hole-spin coherence are limited due to noisy quantum effects, and there is a significant need for further evaluation and investigation studies. In this work, the behavior of charge noise and spin noise for a fundamental logic unit of four qubit embedded in an AlAs/GaAs heterostructure is reported based on the modeling and simulation approach in the atomic level to provide a more in-depth analysis and evaluation of quantum noise. The numerical calculations are based on reliable simulation methods, which are consistent with experimental results. The approach presented here can become the basis for scaled-up advanced simulations expanding to larger logical blocks of qubits.

Multi-Port Memory Design in Quantum Cellular Automata Using Logical Crossing

Memory and its data communication are very significant in the Processor design and its performance. In order to attain high performance computing machine, the memory access has to be equally faster. Here in this paper, Dual port memory with Set/Reset is designed using Majority Voter in Quantum-dot Cellular Automata (QCA). Dual port memory consists of basic functional blocks such as 2 to 4 decoder, Control Logic Block (CLB), Address Checker Block (ACB), Memory Cell (MC), Data Router block and Input / Output block. These functional units are constructed using the 3-input majority voters. QCA is one of the recent technologies for nano-metric design of digital components. The functional simulation of Dual Port Memory design is verified using QCA. A novel crossover method called Logical Crossing is utilized to improve the area of the proposed design. The logical crossing does the data transmission with the support of proper Clock zone assignment. The logical crossing based QCA layouts are optimized in terms of area and number of cell counts. It is observed that 29.81%, 18.27%, 8.32%, 11.57% and 3.69% are percentage of improvement in number of cells in Decoder, ACB, CLB, Data Router and Memory Cell respectively. Also, 25.71%, 16.83%, 8.62%, 4.74% and 3.73% of improvement in area for Decoder, ACB, CLB, Data Router and Memory Cell respectively. In addition to that the proposed Dual port memory using logical crossing attains 8.26% of area and 8.65 % of number of cells improvement. Moreover, the quantum circuits of the RAM are obtained and quantum cost, constant inputs, number of gates, garbage output and total cost are estimated as 285, 67, 57, 50 and 516 respectively.

Augmenting protection coordination index in interconnected distribution electrical grids: Optimal dual characteristic using numerical relays

One of the most significant tasks of protection coordination of power networks is the satisfaction of coordination between protective equipment. With growing penetration level of distributed generations)DGs), selectivity issue of overcurrent relays is very imperative in active distribution systems .Therefore, sustainable electricity needs to enhance the protection coordination index (PCI). These enhancement will cause the development of DG penetration in power networks. In this paper, time-current-voltage characteristics and dual-setting directional overcurrent relays (DOCRs) are jointly deployed to improve PCI in interconnected distribution networks where the coordination process seems a complex problem. Dual-setting relays can trip in forward and reverse directions with individual settings in both directions which provide proper flexibility to improve PCI. Also, time–current-voltage characteristics employ the voltage parameter in operation time of relays which can decrease the optimization process to cause higher flexibility in the coordination process. besides, the mentioned protection model is developed by user-defined time–current-voltage characteristics to improve PCI. The suggested scheme is modeled and presented as a nonlinear programming approach that is tackled by the genetic algorithm (GA) and comparing performance with Grey Wolf Optimization (GWO). In this paper, to evaluate the performance and scalability of the proposed method, IEEE 14-bus and 30-bus system is applied. The advantage of the proposed scheme is the ability to implement in numerical relays, in which paper is expressed in the form of protection logic and description of respective logic blocks. Results depict the significant improvement in PCI.

ТЕОРЕТИКО-МЕТОДОЛОГІЧНИЙ БАЗИС СОЦІАЛЬНО-ЕКОНОМІЧНОЇ ВЗАЄМОДІЇ СУБ’ЄКТІВ ГОСПОДАРЮВАННЯ В УМОВАХ ГЛОБАЛЬНИХ ВИКЛИКІВ

Formulation of the problem. Modern global challenges and imbalances necessitate cooperation in new realities, change the interaction nature to counter global challenges by activating the most effective forms, methods, types and mechanisms of interaction and creating a new values philosophy and motivational guidelines for socio-economic interaction. The processes of socio-economic uncertainty of economic prospects in the context of global challenges require the formation of theoretical and methodological basis for the economic entities interaction. The aim of the research is formation of theoretical and methodological basis for economic entities socio-economic interaction in the context of modern global challenges. The subject of the research is theoretical aspect and methodological aspect of business entities socio-economic interaction in global challenges context. The methods of the research: historical method, methods of verification of theoretical positions (morphological analysis of the content and interrelation of categories, principles and laws, assessment of historical facts to theoretical hypotheses), methods of analysis and synthesis, induction and deduction, logical method (hypothetical and axiomatic approach), comparison method. The hypothesis of the research. In the context of global challenges, it is necessary to change the nature of interaction, for which it is necessary to form a theoretical and methodological basis for such interaction and determine the directions of necessary changes in interaction. The statement of basic materials. Within the epistemological field of research, the definitions of "interaction" as social, economic, philosophical, psychological and managerial categories are analyzed. The providing subsystems of business entities social and economic interaction in the conditions of global challenges are determined, among which the normative and legal, financial, logistical, personnel, informational, logistic, infrastructural, psychological, scientific, institutional, organizational supporting subsystems are singled out and characterized. Within the content (paradigmatic and methodological) basis of the research, it is proposed to distinguish the paradigmatic provisions of socio-economic interaction and the methodological basis of business entities socio-economic interaction research in the context of global challenges. The originality and practical significance of the research. The research of business entities socio-economic interaction in the context of global challenges includes four interrelated blocks – theoretical and explanatory basis of interaction, content (paradigmatic and methodological), applied and managerial basis of interaction, which complex covers possible interaction aspects. Conclusions and perspectives of further research. The article considers the theoretical and methodological basis of business entities interaction during global challenges, within which the implementation of the relevant logical blocks is proposed. Within the framework of further research it is planned to develop an applied basis of interaction, which will provide a diagnostic and prognostic field of socio-economic interaction in the context of global challenges and modeling of of business entities socio-economic interaction, as well as management basis of interaction of business entities, which will provide a sequence of management stages of the socio-economic interaction process and determine the interaction effectiveness in global challenges.

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.

Tunable Sub Threshold Logic Design Through Adaptive Feedback Equalization

An Efficient tunable subthreshold logic circuit planned by utilizing adaptive feedback equalization circuit. This circuit utilized in the Ladner Fischer adder. This circuit utilized in a successive advanced logic circuit to moderate the cycle variety impacts and lessen the prevailing spillage energy part in the subthreshold area. Feedback equalizer circuit changes the switching edge of its inverter. It depends on the output of the flip-flop in the past cycle to lessen the charging and releasing season of the flip-flop's information capacitance. Besides, the more modest info capacitance of the feedback equalizer lessens the switching season of the last door in the combinational logic block. Likewise present point by point energy-performance models of the adaptive feedback equalizer circuit.

BM-RCGL: Benchmarking Approach for Localization of Reliability-Critical Gates in Combinational Logic Blocks

Accurate and effective localization of reliability-critical gates (RCGs) is one of the important prerequisites for low-cost circuit fault tolerance in the early stages of circuit design. This article introduces an accurate and effective approach for localizing RCGs in combinational logic blocks through a benchmarking technique. In the proposed approach, uniform non-Bernoulli sequences are used to produce a set of input vectors for driving circuits. A full-period linear congruential algorithm is employed to generate a sequence that provides the sampled order for the RCGs to be analyzed. This ensures that each gate in the circuit is treated as fairly as possible. To accelerate the localization process, an input-vector-based pruning technique combined with a counting method is also introduced to identify the specified number of RCGs. Then, the criticality of gate reliability for each RCG is measured through benchmarking. A clustering algorithm carries out the convergence checking for the proposed approach. The performance of the proposed approach was evaluated in terms of accuracy, stability, and time-space overhead by various simulations on 74-series circuits and ISCAS-85 benchmark circuits. The results show that its accuracy is close to that of the Monte Carlo model and its stability is better than that of other approximate methods. Moreover, compared with approximate methods, the time overhead of our approach is advantageous in the presence of similar memory overheads.

Logical minimization for combinatorial structure in FPGA

The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA. Programs are designed for shared and separated function minimization in a disjunctive normal form (DNF) class and minimization of multilevel representations of fully defined Boolean functions based on Shannon expansion with finding equal and inverse cofactors. The graphical form of such representations is widely known as binary decision diagrams (BDD). For technological mapping the program of "enlargement" of obtained Shannon expansion formulas was applied in a way that each of them depends on a limited number of k input variables and can be implemented on one LUT-k – a programmable unit of FPGA with k input variables. It is shown that a preliminary logic minimization, which is performed on the domestic programs, allows improving design results of foreign CAD systems such as Leonardo Spectrum (Mentor Graphics), ISE (Integrated System Environment) Design Suite and Vivado (Xilinx). The experiments were performed for FPGA families’ Virtex-II PRO, Virtex-5 and Artix-7 (Xilinx) on standard threads of industrial examples, which define both DNF systems of Boolean functions and systems represented as interconnected logical equations.

ACCOUNTING COMPLIANCE: AN INSTITUTIONAL APPROACH TO ENSURE THE QUALITY OF ACCOUNTING INFORMATION OF THE ENTERPRISE

The subject of the study is theoretical, methodological and practical aspects of the formation, development and functioning of the accounting compliance system as an appropriate institution for ensuring the quality of enterprise accounting information. Methodology. The methodological basis of the study is general scientific and special methods of cognition. In the course of the study, the following methods were used: abstract-logical method was used for the cognition of the essence, approaches, clarification of the concept of “compliance”, “accounting compliance”; bibliographic method was used for the study and development of scientific works devoted to the definition of the essence of the term “compliance”; graphic method was used for the design of the described processes using logical block diagrams; system-structural analysis was used to improve the mechanism for the formation and implementation of the accounting compliance system as an institution for ensuring the quality of accounting information. The objective of the study is to consider the essence of the concept of “compliance”, “accounting compliance”, to establish and define the role of accounting compliance in ensuring the quality of accounting information, to substantiate methodological approaches and practical recommendations for its formation and implementation at the enterprise. Results. The study has established that the definition of “compliance” should include an institutional approach, i.e. “compliance” should be understood as an institution of the internal control and corporate ideology system, which, using a system of regulations and a set of control mechanisms, forms the company’s ability to comply with established norms, standards, rules and procedures; a means of propaganda aimed at promoting the requirements for compliance with internal regulatory documents and generally accepted social values of the enterprise; a set of measures aimed at identifying risks accompanying the activities of the enterprise and eliminating their adverse consequences. “Accounting Compliance” is an institution of the internal control and corporate ideology system of the enterprise, which with the help of a system of measures and a set of control mechanisms provides the ability to track, monitor, evaluate and comply with the requirements of regulatory documents, regulations, instructions in the accounting system. It must be necessarily aimed at identifying, reducing and eliminating the risks of distortion, misrepresentation and falsification of accounting information. It has been substantiated that the accounting compliance system, as an appropriate institution, should be formed in stages, based on a set of specially developed internal methods, rules and procedures. It has been proved that most of the actions of the compliance system are aimed at identifying, analysing and assessing risks in the accounting system, and a significant number of documents defining its normative content are closely related to the implementation of the risk management function. Practical implications. In order to ensure the identification of compliance risks in the company’s accounting system and determine their impact on the formation and quality of accounting information, the grouping of risks by type is presented. To implement the functions of accounting compliance, it was proposed to develop and approve a number of internal standards and regulations, which will guide the employees of the Compliance Department in their work. In order to ensure the quality of accounting information to users necessary for making effective management decisions, the organizational and economic mechanism of the accounting compliance system has been developed. Conclusion of the study. Thus, accounting compliance, as an institution for ensuring the quality of accounting information at an enterprise, should be focused on finding, identifying, assessing, analysing and taking measures to minimize compliance risks in the accounting system arising from non-compliance with established rules, standards and procedures for organization and maintenance of accounting. Substantiated methodological foundations and recommendations for the formation and implementation of accounting compliance will not only ensure the quality of accounting information, but also guarantee business purity, a high level of corporate culture. The latter will contribute to improving the efficiency of economic activities and sustainable development of the enterprise.

Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting

This paper presents an energy-efficient hardware accelerator for binarized convolutional neural networks (BCNNs). In this BCNN accelerator, a data-shift operation becomes dominant to effectively control input/weight-data streams under limited memory bandwidth. A magnetic-tunnel-junction (MTJ)-based nonvolatile field-programmable gate array (NV-FPGA), where the amount of stored-data updating is minimized in a configurable logic block, is a well-suited hardware platform for implementing such a BCNN accelerator. Owing to the nonvolatile storage capability of the NV-FPGA, not only power consumption in the data-shift operation but also standby power consumption in the idle function block is reduced without losing internal data. It is demonstrated under 45 nm complementary metal–oxide–semiconductor/MTJ process technologies that the energy consumption of the proposed BCNN accelerator is 50.7% lower than that of a BCNN accelerator using a conventional static-random-access-memory-based FPGA.

Digital-to-time converter for test equipment implemented using FPGA DSP blocks

This paper presents a novel digital-to-time converter (DTC) implemented using digital signal processing (DSP) blocks built in field-programmable gate array (FPGA) devices. The converter was implemented in a low-cost Xilinx Spartan-6 FPGA chip manufactured in the 45 nm CMOS process and can be applied in any other programmable logic device that contains DSP blocks. The designed DTC time interval jitter is below 2.8 ps. This is the lowest time interval jitter so far reported in such kind of circuits implemented in a programable device. The obtained resolution of up to 8.6 ps is about twice as good as that achieved in a single carry-chain-based delay-line. Furthermore, the designed circuit saves FPGA general-purpose logic (programmable logic blocks). This kind of converter can be especially useful as a part of test instrumentations as well as time-domain signal processing systems implemented in the latest generation of programmable logic devices.

Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block to push these limits and to obtain benefits from this technique in small capacitances. Finally, we proposed to use a stepwise driver in the driving of the gate capacitance of power switches in switched-capacitor (SC) DC–DC converters. We designed and manufactured, in a 130 nm process, a SC DC–DC converter and measured a 29% energy reduction in the gate-drive losses of the converter. This accounts for an improvement of 4% (from 69 to 73%) in the overall converter efficiency.

Gender characteristics of primary school students’ success in solving tasks in the context of varying extrinsic motivational attitudes

The article presents the results of an empirical study of specific characteristics of the success of boys and girls of primary school age in solving convergent problems under the condition of varying motivational attitudes. The study was conducted in the elementary school of the State Budgetary Educational Institution of Moscow “School No. 1561” educational complex in 2016-2018. The study sample includes 239 second-grade students the average age of whom was 8.2 years old. 137 of the study participants were boys and 102 were girls which constitutes 57% and 43% of the sample, respectively. Motivation is assessed via the authors’ modification of N.V. Elfimova’s method “A ladder of motives”, a version of M. Seligman’s Children’s Attributional Style Questionnaire (CASQ) modified by N.A. Baturina and D.A. Tsiring, and the authors’ modification of C. Dweck’s Implicit Theory Scale. The study of the cognitive sphere of the primary school students involves J. Raven’s progressive matrices test, P. Torrance’s test of creative thinking, and E.E. Tunik’s adaptation of J. Johnson’s creativity scale. Within the framework of the experiment, two blocks of convergent tasks are formed: one including non-verbal transitivity tasks (the logical block) and the other containing volumetric and spatial thinking tasks (the spatial block). It is established that the success of primary school students of both sexes in solving convergent tasks is associated not only with the extrinsic motivational attitude constructed through verbal instruction but also with the specific psychological characteristics of the development of the cognitive and motivational spheres in children. The relationship between the success in solving convergent tasks and the psychological characteristics of cognitive development and the motivational sphere differs for boys and girls of primary school age which manifests most intensely in the level of development of the non-verbal component, the leading motivation, and the specifics of the development of the attributional style of explaining success and failure, as well as its particular components.

WITHDRAWN: Optimizing FPGA logic block architectures for self-repairing hardened arithmetic

Hardened adder and carry logic is broadly utilized in business FPGAs to increase the effectiveness of arithmetic capacities. There are various plan conclusions and difficulties related to hardening, including circuit design, FPGA architectural decision and CAD stream. The paper offers an area productive hardened error-tolerant full adder design which is capable of self-repairing both single and double error issues, devoid of disturbing the typical activity of the design. The correlation findings of the proposed technique are well shown to guarantee their potential for boss presentation as compared to the existing hardened adder design.

Merging and Prioritizing Optimization in Block I/O Scheduling of Disk Storage

I/O merging optimization at the block I/O layer of disk storage is widely adopted to reduce I/O response time. But it may result in certain overhead of merging judgment in the case of a large number of concurrent I/O requests accessing disk storage, and place negative effects on the response of small requests. This paper proposes a divide and conquer scheduling scheme at the block layer of I/O stack, to satisfy a large number of concurrent I/O requests with less I/O response time and ensure the fairness of each request response by decreasing the average I/O latency. First, we propose a horizontal visibility graph-based approach to cluster relevant block requests, according to their offsets (i.e., logic block numbers). Next, it carries out the optimization operation of merging consecutive block I/O requests within each cluster, as only these requests in the same cluster are most likely to be issued by a specific application. Then, we have introduced the functionality of merging judgment when performing merging optimization to effectively guarantee the average I/O response time. After that, the merged requests in the queue will be reordered on the basis of their priorities, to purposely cut down the average I/O response time. Finally, the prioritized requests are supposed to be delivered to the disk storage, for being serviced. Through a series of experiments, we show that compared to the benchmark, the newly proposed scheme can not only cut down the I/O response time by more than 18.2%, but also decrease the average I/O response time up to 71.7%.

Applying simulation in lean service to enhance the operational system in Indian postal service industry

This paper aims to present an innovative approach to design a Lean Service System in the India Post service industry using the Simulation method to reduce the system’s complexity. Using logic and systematic building blocks, simulation models have been developed from lean service elements using the arena software and verified in Siemens Tecnomatix plant simulation suite. Simulation is used to replicate the real model, guide the future production system, and determine the optimal parameter values. Simulation studies have been divided into two perspectives, “before LS” and “after LS” through Value Stream Mapping (VSM). It has been found that there is a 9.62 percent enhancement in delivering articles per person. A real case of postal service internal operational performance has been taken for the study. This study is the first to combine Value Stream Mapping - Simulation (VSM-Sim) to simulate and optimize the mailing service operations’ operational performance parameters.