Logic Blocks Research Articles

Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks

Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks

Analysis of models and development of a software package for assessing the impact of vibration effects of vehicles on urban infrastructure

The direction associated with the construction and research of models that can be used to predict the impact of vibration effects of vehicles on surrounding infrastructure facilities is relevant given the increasing pace of civil engineering in large cities and taking into account the expansion of transport networks. The development of models for evaluating vibration effects and for subsequent use in monitoring and diagnostic systems requires the use of modern methods of nonlinear analysis, discrete mathematics, as well as tools for the development of expert systems and artificial intelligence technologies. The purpose of the article is to obtain the results of the analysis of a complex mathematical model of spatial interactions, the development of algorithmic support and a description of the structure of a software package for assessing the impact of vibration effects of vehicles on urban infrastructure. A model of spatial interactions is proposed to assess the levels of vibration exposure with the construction of a graph of the placement of objects connected by vibration propagation channels and using the mathematical apparatus of modeling hybrid dynamic systems, expert knowledge and fuzzy rules of logical inference. Examples of constructing a model of spatial interactions taking into account three objects of vibrational observation are considered. The VibCalcAlg algorithm has been developed to calculate the states of a three-component model. The structure of the VibCalc software package is described, which includes a block of fuzzy logic, a block of model construction and a block of visualization. The results can be used in solving mathematical modeling problems related to the assessment and prediction of vibration impacts in the field of transport and civil engineering, as well as in solving environmental protection problems. The results are aimed at improving intelligent monitoring systems and decision support systems in the design, construction and operation of transport facilities.

Методические подходы к принятию эффективных инвестиционных решений

Achieving the sustainable development goals is a strategic guideline for the national economies of most coun-tries, which is embodied through the formation of socially oriented investment and stimulating the involvement of socially oriented stakeholders in the investment process. The strengthening of this involvement manifested in the interaction of the state, business entities and development institutions in the implementation of socially oriented investment projects, which inevitably requires the development and practical application of special methodological approaches to making investment decisions. The authors substantiate the necessity of apply-ing the methodology of dynamic assessment of the effectiveness of investment decision-making in the man-agement of socially oriented investment projects, as well as develop a chain of creating effective investment decisions as a management tool consisting of several logical blocks and allowing to regulate a consistent re-quired set of investor's actions with the aim of achieving the planned results.

Mathematical formula detection in document images: A new dataset and a new approach

Most of existing mathematical formula detectors focus on detecting formula entities through object detection or instance segmentation techniques. However, these methods often fail to convey complete messages due to the absence of the contextual and layout information of mathematical formulas. For a more comprehensive understanding of mathematical formulas in document images, it is preferable to detect logical formula blocks that include one or multiple formula entities arranged in their natural reading order. These logical formula blocks enable the transmission of complete contextual messages of mathematical formulas and aid in the reconstruction of layout information of the document images, resulting in a more accurate mathematical formula detection. In this paper, we present a novel perspective on mathematical formula detection by framing it as a joint task of formula entity detection and formula relation extraction for identifying logical formula blocks. To this end, we introduce a new, large-scale dataset, called ArxivFormula, that includes well-annotated formula entity bounding boxes and formula relationships. We also propose a new approach, called FormulaDet, to address these two sub-tasks simultaneously. FormulaDet first employs a dynamic convolution-based formula entity detector, named DynFormula, to detect formula entities. It then uses a multi-modal transformer-based relation extraction method, named RelFormer, to group these detected formula entities into logical formula blocks. Extensive experiments on standard benchmarks in this field and the proposed dataset demonstrate that our FormulaDet can achieve significantly improved performance on formula entity detection and formula relation extraction compared to previous state-of-the-art methods. The joint detection and relation extraction approach provides a more thorough understanding of mathematical formulas in document images and effectively supports downstream tasks such as document layout analysis and scientific document digitization. The ArxivFormula dataset is publicly available at https://github.com/microsoft/ArxivFormula.

Analysis of User Behavior using Set-Top-Box for Internet Protocol Television-Based Application

The growth of Internet usage has grown day by day. Many people use the internet for their commercial, education, and personal needs. Misuse of the internet has also increased exponentially. As with the rapid growth of Internet Protocol Television (IPTV), a high alarm still prevails. Much fake news and information are propagated through social media, which misguides many people. Hence tracing back of IP address is needed for appropriate monitoring. The log history stored in the service provider does not enrich the parents to monitor the same. Cache memory involved in the service provider is shared with needy people at their request. Retaining information in service providers depends upon the local norms of any region. A large amount of data handling in the service provider increases the challenges. This paper aims to save the on-view channel IP address in the local Set-Top Box (STB), where STB acts as the front device for IPTV applications. The IP address, including the monitoring frequencies and time observed, is stored in the local STB. This facilitates the parents to monitor their wards, and misuse of the internet is also minimized. The logic block added to the onboard increases the chip area by 3.97m3, and the delay is 847 ps.

Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits using Quantam-Dot Celluar Automata (QCA) Technique

Abstract: In this paper, we propose an approximate multiplier that is Approximate computing (AC) offers benefits by reducing the requirement for accuracy, thereby reducing delay. The majority logic (ML) gate functions as the fundamental logic block of many emerging nanotechnologies. These adders are designed to prevent the propagation of inexact carry-out signals to higher order computing parts to enhance accuracy. We implemented the proposed multiplier by using a unique partial product reduction (PPR) circuitry, which was based on the parallel approximate 6:3 compressor. The implemented by quantum-dot cellular automata (QCA) are analyzed to evaluate the adder designs. A significant improvement is observed over previous designs based on the experimental results. The proposed design is further designed using kogge stone adder. Finally, It has added advantage that reduces logic size and facilitates with less power and delay. Here we are using Verilog HDL and Xilinx ISE14.8 software tools for simulation and synthesis purpose

Self-Checking Combinational Devices Synthesis Based on the Boolean Signal Correction Method Using Bose—Lin Codes

An organizing concurrent error-detection (CED) circuit new method for automation and computer technology combinational device is considered. The method based on the signal's Boolean correction method. The author proposed to use separable codes in the CED circuit synthesis when converting values from all operational outputs of the diagnosing object. The proposed approach allows to consider many possible transformations for each input combination. In addition, it will allow to choose the transformations to provide the conditions for building a completely self-checking device. In comparison with the methods previously discussed in the literature, the proposed approach makes it possible to synthesize a large number of control logic devices in the CED circuit and choose the most appropriate option. For example, with the technical implementation complexity lowest indicators. An algorithm for synthesizing the control logic block is given on the example of using a separable Bose — Lin code with module M = 4 by the signals Boolean correction method when organizing an CED circuit. The proposed method advantages and disadvantages for the CED circuit synthesis are described.

Optimization of a Mealy Automaton Circuit in a Mixed Element Basis

Introduction. The control device is one of the most important blocks of any digital system. The main function of the control device is to coordinate the interaction of the remaining units of the system. Therefore, the characteristics of the control device circuit have a significant impact on the quality of the overall system. To represent the law of functioning of the control device, the models of the microprogrammed automaton (MPA) by Moore and Mealy are used. When synthesizing MPA circuits, it is necessary to solve a number of optimization problems: reducing hardware costs, increasing performance, minimizing power consumption, and jointly optimizing hardware-time characteristics. Methods for solving these problems largely depend on the elemental basis used. Currently, one of the main bases in which modern digital systems are implemented is the FPGA. The main blocks in the FPGA are configurable logic blocks, a programmable interconnect matrix, a timing tree, and programmable inputs and outputs. To implement MPA schemes, two types of configurable logic blocks can be used: tabular logic elements (TLE) and built-in memory blocks (VBP), which have the property of reconfiguration. However, VBPs are widely used to implement various operating blocks of digital systems. Therefore, the controller circuit designer can use a limited number of such memory blocks. Purpose of the article. The article deals with the issues of MPA synthesis when there are a limited number of "free" blocks of EBP. In this case, the microprogram automaton circuit is represented by a network consisting of VBP and TLE blocks. A method for the synthesis of a microprogram automaton with optimization of the number of TLEs is proposed when only one VBP can be used in the microprogram automaton circuit. The proposed method is based on the use of a built-in memory block that performs the replacement of input variables and the coding of the automaton outputs. Results. Studies of the effectiveness of the proposed method were carried out on standard machines. FPGAs of the Virtex-7 family from Xilinx were used as the elemental basis. To implement the proposed MPA, the Vivado package was used. The results of the research showed that the use of the VBP block made it possible to reduce the number of SLE blocks by an average of 14 % – 18 % compared to schemes consisting only of SLE. For the Virtex-7 family FPGA, the number of TLE inputs Io= 6 was sufficient for a single-level implementation of the output system. Conclusions. The effectiveness of the proposed method makes it possible to recommend it for use in the synthesis of microprogram automata under conditions of an extremely limited number of BVPs. Keywords: Mealy automaton, synthesis, coding of inputs, coding of sets of outputs.

Improving Characteristics of FPGA-Based FSMs Representing Sequential Blocks of Cyber-Physical Systems

This work proposes a method for hardware reduction in circuits of Mealy finite state machines (FSMs). The circuits are implemented as networks of interconnected look-up table (LUT) elements. The FSMs with twofold state assignment and encoding of output collections are discussed. The method is based on using two LUT-based cores to implement systems of partial Boolean functions. One of the cores uses only maximum binary codes, while the second core is based on the use of extended state codes. The hardware reduction is based on diminishing the number of transformed maximum binary codes. This leads to FPGA-based FSM circuits with three levels of logic blocks. Each logic block has a single level of LUTs. As a result, partial functions are represented by single-LUT circuits. The article shows a step-by-step procedure for the transition from the initial form of the FSM representation to its logical circuit (a network of programmable look-up table elements, flip-flops, and interconnects). The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based FSM circuits with significantly better area characteristics than for circuits produced by such methods as Auto and One-Hot of Vivado, JEDI, and twofold state assignment. Compared to these methods, the number of LUTs is reduced from 9.44% to 69.98%. Additionally, the proposed method leads to the following phenomenon: the maximum operating frequency is slightly improved as compared with FSM circuits based on twofold state assignment (up to 0.6%). The negative effect of these improvements is an increase in power consumption. However, it is extremely insignificant (up to 1.56%). As the values of the FSM’s main characteristics grow, there is an increase in the gain from the application of the proposed method. The conditions for applying the proposed method are determined. A generalized architecture consisting of three blocks of partial functions and a method for synthesizing an FSM with this architecture are proposed. A method for selecting one of the seven architectures generated by the generalized architecture is proposed.

Analytical Placement with 3D Poisson’s Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs

As design complexity keeps increasing, the 2.5D field-programmable gate array (FPGA) with large logic capacity has become popular in modern circuit applications. A 2.5D FPGA consists of multiple dies connected through super long lines (SLLs) on an interposer. Each die contains heterogeneous logic blocks and ASIC-like clocking architectures to achieve better skew and timing. Existing works consider these problems separately and thus may lead to serious timing issues or routing failure. This article presents an analytical placement algorithm for the 2.5D FPGA to simultaneously minimize the number of inter-die SLL signals and intra-die clocking violations. Using a lifting dimension technique, we first formulate the 2.5D global placement problem as a three-dimensional continuous and differential minimization problem, where the SLL-aware block distribution is modeled by 3D Poisson’s equation and directly solved to obtain an analytical solution. Then, we further reformulate the minimization problem as a separable optimization problem with linear constraints. Based on the proximal alternating direction method of multipliers optimization method, we efficiently optimize the separable subproblems one by one in an alternating fashion. Finally, clock-aware legalization and detailed placement are applied to legalize and improve our placement results. Compared with the state-of-the-art works, experimental results show that our algorithm can resolve all clocking constraints and reduce the number of SLL crossing signals by 36.9% with similar wirelength in a comparable running time.

Efficient classification and preservation of log integrity through propagated chain in cloud

Preserving the integrity of log data and using the same for forensic analysis is one of the prime concerns of cloud-oriented applications. Since log data collates sensitive information, providing confidentiality and privacy is of at most importance. For data auditors, maintaining the integrity of the log data is a prime concern. Existing models focus on providing models and frameworks that relies on any third-party entity or the cloud service provider (CSP) to handle the logs, which lacks in securing the integrity due to the presence of the external entities. Sole dependence on CSP is a major flaw together with a drawback, since the CSP itself is prone to data theft alliance. In this paper, we instantiate a mechanism which maintains the integrity of the log without compromising the performance efficiency of the system. The influence of machine learning classification techniques is leveraged in order to efficiently classify the log data before it is processed. Progressively the log data integrity is maintained through the proposed Propagated Chain of Log Blocks (PCLB), the Hybrid Vector Committed BST (HVCBST) and lightweight Multikey Hybrid Storage (MKHS) structures. The results of the implemented systems have proven to be efficient and tamper proof compared to the existing systems and can be easily rendered in any private or public cloud deployments.

CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration

Block random access memories (BRAMs) are the storage houses of FPGAs, providing extensive on-chip memory bandwidth to the compute units implemented using logic blocks and digital signal processing slices. We propose modifying BRAMs to convert them to CoMeFa ( Co mpute-in- Me mory Blocks for F PG A s) random access memories (RAMs). These RAMs provide highly parallel compute-in-memory by combining computation and storage capabilities in one block. CoMeFa RAMs utilize the true dual-port nature of FPGA BRAMs and contain multiple configurable single-bit bit-serial processing elements. CoMeFa RAMs can be used to compute with any precision, which is extremely important for applications like deep learning (DL). Adding CoMeFa RAMs to FPGAs significantly increases their compute density while also reducing data movement. We explore and propose two architectures of these RAMs: CoMeFa-D (optimized for delay) and CoMeFa-A (optimized for area). Compared to existing proposals, CoMeFa RAMs do not require changing the underlying static RAM technology like simultaneously activating multiple wordlines on the same port, and are practical to implement. CoMeFa RAMs are especially suitable for parallel and compute-intensive applications like DL, but these versatile blocks find applications in diverse applications like signal processing and databases, among others. By augmenting an Intel Arria 10–like FPGA with CoMeFa-D (CoMeFa-A) RAMs at the cost of 3.8% (1.2%) area, and with algorithmic improvements and efficient mapping, we observe a geomean speedup of 2.55× (1.85×) across microbenchmarks from various applications and a geomean speedup of up to 2.5× across multiple deep neural networks. Replacing all or some BRAMs with CoMeFa RAMs in FPGAs can make them better accelerators of DL workloads.

An FPGA-Based Reconfigurable FIR Filter for SDR Applications

This article presents a proposal of a reconfigurable FIR filter capable of covering the most common wireless communication standards on software-defined radio applications. The filter was implemented using a low-cost field programmable gate array, Cyclone IV EP4CE22F17C6 model from Altera®. System design is presented together with simulation results. Validation is done for a 500 kHz base-band noisy signal. The synthesized design uses 5,259 logic elements of which 4,778 were used for combinational logic blocks and 513 for dedicated logic registers, which represents 22% of total used FPGA capacity. The maximum sampling frequency supported by the architecture is 23.24 MHz.

12-nm Stable Pre-Amplifier Physical Unclonable Function With Self-Destruct Capability

Physical unclonable functions (PUFs) produce full security keys without needing to store the key directly in nonvolatile memory (NVM) or publicly. PUFs rely on a stable entropy source across voltage, temperature, and lifetime. A high-gain preamplifier (Pre-Amp) bit cell was built into a dense 2-D array configured as 16 cells per bitline (BL) and 64 cells per wordline (WL). A hardware (HW) sample of 40 chips (1 Kb/chip) was manufactured in GLOBAL FOUNDRIES (GF) 12-nm (12 lp) CMOS technology for a total raw bit count of 40 960 bits. HW characterization was performed to support power supply ranging from 0.7 to 1.0 V and junction temperatures ranging from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 40 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C to 125 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C with a worst case bit error rate (BER) of 0.174% after stabilization. The entropy source array is complete for productization with control logic and analog power system block for process, voltage, and temperature (PVT) compensation. A stable bit identification and sensing circuit is designed to identify bit cells that are robust against varied test conditions. The NIST 800-90B test suite was run on the native array and stable entropy source bits with minimum entropy scores of 0.65/bit and 0.697/bit, respectively. This article then introduces for the first time ever the ability for a PUF key to be corrupted and physically destroyed, which can be utilized to stop a tamper event or to corrupt obsolete chips. In the self-destruct (SD) mode, the entropy source data can be irreversibly destroyed, blocking all future authentication attempts. HW data show the before and after SD bitmaps, where electromigration (EM) physically breaks the connection of the entropy source bit cells from the sensing circuits. A safety lock circuit is also included to prevent inadvertent SD.

FUZZY-LOGIC MODELING OF TEMPERATURE REGIMES IN THE PROCESSES OF RADICAL SUSPENSION POLYMERIZATION

An approach to the synthesis of neuro-fuzzy models of temperature regimes of industrial reactors for polymer synthesis is proposed for consideration. The expediency of developing such a model is justified by its subsequent application in intelligent robust-adaptive automatic control systems as a reference model for generating control signals. The basis for constructing a fuzzy model of the reactor is an array of data obtained as a result of conducting many experiments on a physical model of a polymer synthesis reactor. Structurally fuzzy model includes three blocks of fuzzy logic. The first block is a fuzzy model of the kinetics of the polymerization process. The output of this block is a monomer conversion curve. The second block of the fuzzy model generates a curve of change in the temperature of the mixture in the reactor normalized to the range [0;1]. This is possible due to the fact that the shape of the temperature change curve depends only on the moment of exhibition of the gel effect, which is inherent in the processes of radical polymerization. This point can be unambiguously determined from the monomer conversion curve. The third block of the fuzzy model calculates the value of the scaling factor based on the current flow rate of the coolant, as well as the set value of the water modulus and the temperature regime in the reactor. After calculating this coefficient, it is multiplied by a normalized curve and the value of the specified temperature regime is added, obtaining at the output the final curve of temperature change in the reactor. The block structure of the proposed fuzzy model is its essential difference from possible analogues and its key advantage. Due to this structure of the model, it is possible to replace, if necessary, some of its elements in order to obtain the possibility of modeling the processes of radical polymerization of different monomers. For citation: Lopatin A.G., Brykov B.A. Fuzzy-logic modeling of temperature regimes in the processes of radical suspension polymerization. ChemChemTech [Izv. Vyssh. Uchebn. Zaved. Khim. Khim. Tekhnol.]. 2023. V. 66. N 6. P. 123-129. DOI: 10.6060/ivkkt.20236606.6682.

Four-Channels High-Resolution Frequency Counter for QCM Sensor Array Using Generic FPGA XC6SLX9 Board

A frequency counter is essential for resonance-based sensors like quartz crystal microbalance. An electronic nose or tongue using a QCM sensor array requires a multichannel frequency counter to detect the frequency shift of the sensors simultaneously. The frequency counter’s resolution, precision, and sampling speed are important factors. Board size, energy consumption, and rapid deployment are also considered in the design. This work shows the development of an independent multichannel frequency counter using a commercial Xilinx Spartan 6 series XC6SLX9 board module and a microcontroller board. Both modules are general-purpose modules; therefore, there is no need for a printed circuit board design, resulting in a quick implementation: the use of FPGA results in a compact size and low energy consumption. The developed counter is designed based on a reciprocal counter utilizing the internal logic block of the FPGA. The FPGA module has a built-in 50 MHz TCXO clock and is the reference clock. The high-resolution timing of the counter is realized by multiplying the 50 MHz clock by 6 to reach 300 MHz. The multiplication utilizes the PLL modules in the FPGA. The high precision and accuracy of the counter are achieved by calibrating the timing clock to a 10 MHz rubidium oscillator. The data communication to the microcontroller is done via the SPI by implementing the SPI protocol in the FPGA. The resource is optimized by utilizing PLL and DSP blocks for the counter. Only 5% registers and 5% LUTs of the FPGA resource are used to build a four-channel frequency counter. The result shows that the counter can measure the frequency of incoming signals with a resolution of 0.033 Hz at 10 MHz with a sampling time of 1 second. The system has been tested to monitor the frequency changes of a QCM sensor array.

Application of the theory of constraints to unveil the root causes of the limited market penetration of micro gas turbine systems

Micro Gas Turbines are small devices for on-site power and heat generation. Their high maintainability and fuel flexibility make them a suitable technology for transitioning to a greener economy. However, their commercialisation did not match the stakeholders’ expectations. The authors applied the Theory of Constraints – a methodology for the continuous improvement of systems – to the MGT industry introducing a structured and rigorous representation. The constraint – i.e. Root Cause – Analysis identified which entities sustain the cause–effect chain, eventually generating the Undesired Effects. The system constraints link to the specificity and effectiveness of commercialisation strategies and product innovation in agreement with evolutionary market theories. Moreover, the Theory of Constraints emphasises the presence of reinforcement loops that make targeting entities like high product costs ineffective. The missing piece to complete the puzzle is solving a logic block representing the product’s market competitiveness depending on economic and technical factors. This study suggests that combining market-driven innovation and commercialisation is likely the only long-term solution to the lack of commercial success of the technology. However, the work also highlights limitations in the proposed methodology and solutions. To tackle these, the authors suggest and introduce numerical frameworks based on the Theory of Constraint.

ИССЛЕДОВАНИЕ ПАРАМЕТРОВ ФИЗИЧЕСКИ НЕКЛОНИРУЕМОЙ ФУНКЦИИ ТИПА АРБИТР ПРИ РЕАЛИЗАЦИИ НА ПЛИС

The influence of various circuitry solutions of a physically unclonable function (PUF) of the arbiter type and the location of their logical blocks on the parameters of the PUF are investigated. The increasing proliferation and use of Internet of Things (IoT) technologies and, accordingly, devices connected to cellular and Internet networks, an urgent problem is to ensure the security and confidentiality of data access. It should be noted that IoT devices are demanding on a number of parameters, such as power consumption, integrated circuit geometric dimensions, and the requirement to protect against cyberattacks. As a simple, cost-effective and universal solution, hardware methods of physical cryptography proved to be the most preferred. Physically unclonable functions can be implemented in various devices by designing their circuits based on field-programmable gate arrays (FPGA). The Xilinx FPGA of the Zynq-7000 family has been used for this study. This approach gives greater flexibility in terms of the architecture used and allows the system to be more precisely adapted to any need. EBAZ4205 and AntMiner_v1.0 FPGA debug boards based on the XC7Z010CLG400-1 platform with two built-in ARM Cortex-A9 processor cores have been used as monitoring and measuring equipment. The method of physical cryptography of devices is considered. Several configuration bitstreams of PUF the arbiter-type firmware with different arrangement of functional blocks on a chip have been developed and implemented. All configurations have been tested, and the results were shown to change depending on the PUF location on the chip. An important task while implementing the PUF of the arbiter type on any hardware platform is to equalize the lengths of the signal propagation lines. This can be achieved both by adding additional delay blocks on the line, and by increasing the length of the routed signal line. In this study the best results were obtained with manual routing and a "vertical" arrangement of the logical blocks of the circuit.

Logical Blocks for Fault-Tolerant Topological Quantum Computation

Logical gates constitute the building blocks of fault-tolerant quantum computation. While quantum error-corrected memories have been extensively studied in the literature, explicit constructions and detailed analyses of thresholds and resource overheads of universal logical gate sets have so far been limited. In this paper, we present a comprehensive framework for universal fault-tolerant logic motivated by the combined need for platform-independent logical gate definitions, flexible and scalable tools for numerical analysis, and exploration of novel schemes for universal logic that improve resource overheads. Central to our framework is the description of logical gates holistically in a way which treats space and time on a similar footing. Focusing on schemes based on surface codes, we introduce explicit, but platform-independent representations of topological logic gates -- called logical blocks -- and generate new, overhead-efficient methods for universal quantum computation. As a specific example, we propose fault-tolerant schemes based on surface codes concatenated with more general low-density parity check (LDPC) codes. The logical blocks framework enables a convenient mapping from an abstract description of the logical gate to a precise set of physical instructions for both circuit-based and fusion-based quantum computation (FBQC). Using this, we numerically simulate a surface-code-based universal gate set implemented with FBQC, and verify that their thresholds are consistent with the bulk memory threshold. We find that boundaries, defects, and twists can significantly impact the logical error rate scaling, with periodic boundary conditions potentially halving the resource requirements. Motivated by the favorable logical error rates for boundaryless computation, we introduce a novel computational scheme based on the teleportation of twists that may offer further resource reductions.

Sharing of Compressed Tests Among Logic Blocks

In a design that consists of several logic blocks, each logic block may be tested separately using its own compressed test set and on-chip decompression logic. The decompression logic is typically based on a linear circuit, such as a linear-feedback shift register (LFSR), and tests are compressed into initial states (seeds). This article observes that even if different LFSRs of different lengths are used for different logic blocks, there is flexibility to select compressed tests that can be shared among the logic blocks. This article describes a test compaction procedure that accepts compact compressed test sets computed for the logic blocks individually. The procedure combines the test sets into a single test set and optimizes it considering all the logic blocks together. This is important for applications where storage of tests is a bottleneck. Experimental results are presented to demonstrate the effectiveness of the test compaction procedure when groups of benchmark circuits are considered as logic blocks in the same design. A procedure for constructing groups with significant sharing of compressed tests is also discussed.