Logic Blocks Research Articles

Использование пентаграммы для структурирования процесса изучения электротехнических устройств

Faster emergence and introduction of the new technologies in the modern world requires changes in the field of engineering education. Large volumes of knowledge must be transferred in a shorter time. In this paper, an alternative view on structuring the process of studying electrical devices is presented, using electrical machines and frequency converters as the examples. It is proposed to use the set of logical blocks, graphically described by a pentagram — a well-known symbol and a geometric figure — for the organization and transfer of the knowledge. It is assumed that this method of knowledge transfer will be more efficient in terms of the time required. A pentagram is a set of related logical, locks that describes a set of physical processes, effects, their connections with each other and, probably, even the philosophy of building the electrical devices.

Technique to Dynamically Reconfigure FPGAs using Control Registers

Due to increased use of FPGAs computation intensive applications, the need for embedded processing system integrated with programmable logic device has also increased. Configuration of programmable logic device by the processing system through its interface improves the efficiency of the device. In order to operate as a stand-alone device and to have a better efficiency, the programmable logic device must be capable of dynamically programming its own configuration memory. In this paper, we propose a configurable logic block with a control register to improve performance of the programmable logic device. The control register acts like a decentralized configuration memory array which can be programmed by other such configurable logic blocks. The FPGAs are fault tolerant devices with repetitive structures requiring high packaging density. This property of FPGA enables the use of CNTFETs for design of FPGAs. CNTFETs offer high trans-conductance and 1-D ballistic transport of electrons and holes which minimizes the power consumed by the FPGA. The proposed control register based architecture was implemented using Cadence Virtuoso using virtual source CNTFET model from Stanford University. A power reduction of 17.62% is achieved using CNTFETs when compared with FINFET at same technology node and the architecture was verified for various configurations of the control register.

Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed–Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression’s construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.

Удосконалення механізму організації природокористування на території басейну Дніпра

It was proved the priority of choosing the principles of rational use of nature, which activates the search for ways of optimizing the use of natural resources and developing effective mechanisms for their reproduction. It has been established the strengthening of anthropogenic-induced degradation of land and water resources of the transboundary Dnipro river basin, which is a key factor in the formation and organization of political, economic and social life of society. It has been determined that rational using of nature is based on the conceptual model of ecological and rational exploitation of the territory of the transboundary basin. It has been developed a methodology of integrated assessment, analysis and forecasting of the ecological state of the catchment area and optimization of land using in rivers basins, which contains six logical and sequential blocks of research organization that provide systematic use of complementary general, adapted and authorial methods. In addition to optimizing the use of natural resources, support should be given to mechanisms for their reproduction through the search of optimal nature using scenarios, which will ensure the effective development of the territories and the restoration of the Dnipro river ecosystem. The principles of activity of the Interstate Basin Council of the Dnipro River and the mechanism of nature protection organization of the territory of the transboundary basin on the basis of improved methodology and author's methods with the use of GIS and Remote sensing of Earth technologies are offered. It was established that the result of the study is the formation of a unified system of parameters of control of the current state of the whole Dnipro river basin, with the obligatory determination of the risks of violations of ecological parameters of the basin landscape structures and determination of their consequences. It was determined that the organization of the catchment area of the Dnipro River requires the transfer to the scientific and legal plane of using the nature with the necessary development of appropriate soil and water conservation measures. The urgency of the planning of the catchment basins on the basis of the balance of environmental sustainability of agricultural landscapes and the intensity of agricultural production in order to maximize profits was determined. The Dnipro river health management system should be based on a comprehensive spatio-temporal analysis of the ecological state of its basin and on the basis of the basin management principle

Power Electronics Education A Contemporary Teaching Appproach

Currently, there is a growing demand for methodologies that best qualify engineering students at universities. These methodologies require a substantial change in Engineering Teaching programs improving or even changing the traditional ways of imparting knowledge to students. In Power Electronics (PE) study the factors that make learning difficult for Electrical Engineering students, in order for them to achieve full understanding of the subjects addressed in a first discipline in this area, are the academic maturity required coupled with their multidisciplinary nature. The problem is aggravated in practical activities, which demand the availability of a laboratory infrastructure with specific characteristics not always available. An alternative for the study of PE, with a more contemporary focus, is to introduce, through a new Instructional Design (ID) Project, not only the incorporation of more Hands-On activities that approach truly meaningful (authentic) contents. But also, new methodologies and technologies to support educational objectives that make full use of Digital Information and Communication Technologies (DICTs).This work proposes to develop and carry out a methodological design of a blended teaching for a power-electronics-based practical training program (PEBPTP) for students of the Electrical Engineering Course of the Federal University of Maranhão in Brazil. The proposed program is mainly based on the use of a digital controller (unified) based on FPGA, developed and realized specifically for control and power inverters study. From controller´s VHDL Code already realized, a Reuse Logic Block is generated (Intellectual Property Core (IP Core)), for use within the LabVIEW FPGA Hardware Description Environment. A Graphical Interface (GUI), more intuitive, and developed from the LabVIEW environment, will support the realization of the PEBPTP, for parameterizing the Controller, and show relevant figures of merit of the performance of the converter being study. The active methodologies, converging with the diverse possibilities of resources of the DICTs, implanted in the classroom, with the adequate contextualization of the specific resources of each area, contribute increasingly to the student being protagonist of their own knowledge construction. Finally is proposed, and in full adherence to a novel trend, that both the PEBPTP and the unified controller previously developed in FPGA are embedded in what is being named Lab-on-a-Chip (LoC). This embedded structure will allow access to the laboratory hands-on program via a web service that uses a fully programmable logic device (PLD) that incorporates an integrated structure known as System-on-a-Chip (SoC). The above proposals and experiences involve the mastery not only of curricular and technological knowledge, inherent to the training of an engineer, but of mainly, the pedagogical technological knowledge and correct use of DICTs. At this point, in particular, is founded our contribution within the context of Engineering Teaching, to advance in the improvement or perhaps in the modification of the "classroom" of engineering courses, which today go beyond the physical space of the university.

Graph of Outputs in the Process of Synthesis Directed at CPLDs

The paper focuses on the methodology of designing a cyber physical systems (CPS) physical layer using programmable devices. The CPS physical layer can be implemented in programmable devices, which leads to a reduction in their costs and increases their versatility. One of the groups of programmable devices are complex programmable logic devices (CPLDs), which are great for energy-saving, low-cost implementations but requiring flexibility. It becomes necessary to develop mathematical CPS design methods focused on CPLD. This paper presents an original technology mapping method for digital circuits in programmable array logic (PAL)-based CPLDs. The idea is associated with the process of multilevel optimization of circuits dedicated to minimization of the area of a final solution. In the technology mapping process, the method of a multioutput function was used in the graph of outputs form. This method is well known from previous papers and proposes optimization of a basic form of the graph of outputs to enable better use of the resources of a programmable structure. The possibilities for the graph of outputs were expanded in the form of sequential circuits. This work presents a new form of a graph that describes the process of mapping and is known as the graph of excitations and outputs. This graph enables effective technology mapping of sequential circuits. The paper presents a series of experiments that prove the efficiency of the proposed methods for technology mapping. Experiments were conducted for various sizes of PAL-based logic blocks and commercially available CPLDs. The presented results indicate the possibility of more effective implementation of the CPS physical layer.

Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan.

MRAM-Enhanced Low Power Reconfigurable Fabric With Multi-Level Variation Tolerance

A hybrid device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. A hierarchical top-down design approach is used to develop a hybrid spin/charge based FPGA (HSC-FPGA) starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication challenges. Circuit-level simulations indicate at least 40% and 83% read and standby power reduction, respectively, for MRAM-LUTs compared to SRAM-LUTs. However, MRAM-LUTs using spin transfer torque (STT) switching approach suffers from significant write energy consumption. Therefore, we have designed spin Hall effect (SHE)-assisted MRAM-LUTs realizing more than 67% and 61% reduction in reconfiguration energy and area consumption, respectively. Fabric-level simulations exhibit that HSC-FPGA achieves 70% and 30% reductions in standby and read power, respectively, compared to SRAM-based FPGAs for various ISCAS-89 and ITC-99 benchmark circuits. Finally, a multi-level method spanning device-sizing, circuit modular-redundancy, and component-level reconfiguration is developed to increase the process variation resiliency of the MRAM-LUTs. The power consumption and area utilization are analyzed to formulate tradeoffs resulting in recommendations toward future multi-device-based reconfigurable fabrics.

Design and Demonstration of an Adiabatic-Quantum-Flux-Parametron Field-Programmable Gate Array Using Josephson-CMOS Hybrid Memories

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient high-performance information processing systems. Its static power is zero because of ac flux bias, and its dynamic power is considerably reduced, thanks to the adiabatic switching of the junctions. The lack of high-density memories in the AQFP logic, however, makes it challenging to realize large-scale information processing systems with the use of pure AQFP circuits. We have been developing a Josephson-CMOS hybrid memory to overcome the memory bottleneck in AQFP digital systems. By utilizing the high sensitivity of the AQFP gate, the output current from CMOS memories can be significantly decreased resulting in the reduction of the power consumption. In this article, we designed and fabricated a low-power area-efficient AQFP-CMOS hybrid field-programmable gate array (FPGA), where a CMOS memory is utilized as a rewritable read-only memory to control the AQFP circuits. The AQFP circuit for the AQFP-CMOS hybrid FPGA is composed of logic blocks, switch blocks, and connection blocks, which are clocked by four-phase excitation currents. The AQFP-CMOS hybrid FPGA is fabricated by using the AIST 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb high-speed standard process and the Rohm 0.18 μm CMOS process. The area and power consumption of the two-by-two AQFP logic-cell system are estimated to be approximately 6.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 12.4 nW at 5 GHz operations, respectively. The power consumption of the CMOS memory was estimated to be 1.02 μW assuming the CMOS source voltage of 3 mV. We demonstrated the operation of the AQFP-CMOS hybrid FPGA at low speed by combining the AQFP logic and the CMOS memory.

Introduction of Basic Computer Programming Logic in Elementary and High Schools Using Logic Block

This document analyzes factors that make it difficult for computational programming logic to consolidate itself as a subject to be taught in schools and how to introduce it into the academic environment through a hypothetical curriculum based on studies and also including the logical block programming language, Scratch. Studies are conducted to create the basis of an experimental school grade. Said grade describes in detail the age groups it will reach and what knowledge will be taught to them. With a better understanding of programming and programming logic in mind, not only individuals who choose to work in the field will already have a larger knowledge base than today, but people who choose not to work in the field of computer technology will benefit of a more logical and cohesive line of reasoning.

7 questions for energy concept in ecosystems science

Seven questions that fall in the gap between economics and the science of physics and chemistry are posed in a search for eventual improved insight into the processes providing ecosystem services. Economics and science are like two different cultures that both began in an era of awe at Newtonian physics. Economics has continued with models based on that while science has made giant steps into new levels of discovery. The paths of scientific revolution have been bumpy and ad hoc, pragmatically resolving technical questions in ways that “work”, sometimes oblivious of the need for elegance that would explain the macroscopic view of ecosystems. Economic analysis of ecosystem services needs to reverse engineer some scientific discoveries, especially the concept behind the term “energy”, and rebuild in logical blocks that embrace a wider boundary with a clearer focus of workings in space and time.

Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates

The RRAM (resistive random-access memory) is one of the most competitive candidates of the emerging non-volatile memory devices. In recent years, the RRAM has been used as memory device and also to build logic circuit. However, the design method of the RRAM-based logic circuit is still an open issue. This paper proposes a design method of logic circuit based on the four-step RRAM logic gates. The design rules are studied for both the combinational and the sequential logic circuits in a parallel style. The design practices and synthesis results show that the proposed methods generate the high-performance circuits for the arbitrary logic functions. Moreover, the four-step RRAM-based logic gates are suitable for designing the circuits with pipelined architecture, since the different RRAM logic blocks have the uniform working speed. The pipelined N-bit ripple carry adder and the N-bit multiplier outperform the other RRAM base counterparts; the output results are obtained only with 2N + 2 and 6N− 4 working cycles, respectively.

A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication

Approximate computing is an emerging approach for reducing the energy consumption and design complexity in many applications where accuracy is not a crucial necessity. In this study, ultra-efficient imprecise 4:2 compressor and multiplier circuits as the building blocks of the approximate computing systems are proposed. The proposed compressor uses only one majority gate which is different from the conventional design methods using AND - OR and XOR logics. Furthermore, the majority gate is the fundamental logic block in many of the emerging majority-friendly nanotechnologies such as quantum-dot cellular automata ( QCA ) and single-electron transistor ( SET ). The proposed circuits are designed using FinFET as a current industrial technology and are simulated with HSPICE at 7nm technology node. The results indicate that our imprecise compressor is superior to its previous counterparts in terms of delay, power consumption, power delay product (PDP) and area, and improves these parameters on average by 32%, 68%, 78%, and 66%, respectively. In addition, the proposed efficient approximate multiplier is utilized in image multiplying as an important image processing application. The HSPICE and MATLAB simulations indicate that the proposed inexact multiplier provides a significant compromise between accuracy and design efficiency for approximate computing.

Synthesis of Built-in Self-Test Control Circuits Based on the Method of Boolean Complement to Constant-Weight 1-out-of-n Codes

We consider the problem of designing a built-in control circuit with full self-testability of control equipment based on the method of Boolean complement to constant-weight 1-out-of-n codes. A method is proposed for determining complementary functions considering the formation of the necessary set of test combinations for a complete check of each element of modulo-2 addition in the structure of the Boolean complement block. Due to the introduction of uncertainties in the selection of values, it is possible to minimize the complexity of control functions, which makes it possible to simplify the control logic block. An algorithm for the synthesis of a built-in self-test control circuit based on the method of Boolean complement to a preselected constant-weight 1-out-of-n code is given.

A New Paradigm for FPGA Placement Without Explicit Packing

Placement and packing are two important but separated optimization steps in a conventional field programmable gate array (FPGA) implementation flow. A packing engine clusters logic elements, like lookup tables and flip-flops, into configurable logic blocks, while a placement engine determines their physical locations in FPGA layouts. This paper presents a new paradigm for FPGA placement without an explicit packing stage. In the proposed framework, the solution spaces of placement and packing are simultaneously explored in a smooth and elegant way. Our experiments on ISPD 2016 and 2017 benchmark suites demonstrate the effectiveness of the proposed framework.

Design of Hybrid LUT/MUX FPGA Logic Architecture for size Reduction and Performance Improvement in FPGA

Hybrid configurable logic block architectures for field-programmable gate arrays that contain a blend of LUT's and solidified multiplexers that are assessed towards the objective of higher rationale thickness and diminished region. Innovation mapping advancements that focus on the proposed models are likewise perform inside Xilinx programming. Both for complex rationale square and steering territory while keeping up mapping profundity, the named engineering of this paper examine the rationale size, region and power utilization utilizing Xilinx 14.5.

Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory

Brain-inspired hyperdimensional (HD) computing models neural activity patterns of the very size of the brain’s circuits with points of a hyperdimensional space, that is, with hypervectors . Hypervectors are D -dimensional (pseudo)random vectors with independent and identically distributed (i.i.d.) components constituting ultra-wide holographic words: D =10,000 bits, for instance. At its very core, HD computing manipulates a set of seed hypervectors to build composite hypervectors representing objects of interest. It demands memory optimizations with simple operations for an efficient hardware realization. In this article, we propose hardware techniques for optimizations of HD computing, in a synthesizable open-source VHDL library, to enable co-located implementation of both learning and classification tasks on only a small portion of Xilinx UltraScale FPGAs: (1) We propose simple logical operations to rematerialize the hypervectors on the fly rather than loading them from memory. These operations massively reduce the memory footprint by directly computing the composite hypervectors whose individual seed hypervectors do not need to be stored in memory. (2) Bundling a series of hypervectors over time requires a multibit counter per every hypervector component. We instead propose a binarized back-to-back bundling without requiring any counters. This truly enables on-chip learning with minimal resources as every hypervector component remains binary over the course of training to avoid otherwise multibit components. (3) For every classification event, an associative memory is in charge of finding the closest match between a set of learned hypervectors and a query hypervector by using a distance metric. This operator is proportional to hypervector dimension ( D ), and hence may take O( D ) cycles per classification event. Accordingly, we significantly improve the throughput of classification by proposing associative memories that steadily reduce the latency of classification to the extreme of a single cycle. (4) We perform a design space exploration incorporating the proposed techniques on FPGAs for a wearable biosignal processing application as a case study. Our techniques achieve up to 2.39× area saving, or 2,337× throughput improvement. The Pareto optimal HD architecture is mapped on only 18,340 configurable logic blocks (CLBs) to learn and classify five hand gestures using four electromyography sensors.

Application-Dependent Testing of FPGA Interconnect Network

The extensive application of field-programmable gate array (FPGA) devices in industrial environments makes FPGA testing a significant area of exploration. The application-dependent testing approach ensures better manufacturing yield compared to the manufacturing testing process since it can bypass the faulty parts without disturbing a given user-defined design. The interconnection resources occupy a large area in the FPGA die, and it is highly error-prone due to the presence of a huge number of transistors. Interconnection resources testing play a major role in the reconfigurable hardware testing area. This paper presents an application-dependent testing technique to generate test configurations for interconnects in static RAM (SRAM)-based FPGAs. To generate a test pattern for interconnects, logic block configurations have been modified. This paper addresses stuck-at faults, different types of dominant bridging faults, and feedback bridging faults. Appropriate constraints have been designed using Boolean satisfiability to test the above faults in the interconnects. Simulations performed on ISCAS’89, MCNC, and ITC’99 benchmark circuits mapped on different FPGA architectures show that the proposed approach can obtain a minimum number of test configurations with 100% fault coverage for the above-mentioned faults and is technology independent which enables it to address new emerging architectures in FPGAs.

Secuenciador dinámico para el control de movimiento de robot hexápodo en una arquitectura FPGA

A hexapod robot control system hardware architecture is presented. The control system is integrated in an FPGA XC6SLX16-Spartan6. The design is developed using hardware description language, VHDL. A robust architecture, divided into three logical state machine blocks, is implemented in the FPGA. Block one consists of a serial communication system for the information interchange between the user and the FPGA. The second block corresponds to the sequential circuit and data manager in charge of controlling the functions of the entire architecture. The third block is an 18-channel PWM pulse generator with a progressive duty cycle change control to perform robot movements. The system is designed to allow the user to download a complex movements sequence by combining different positions and waiting times. The architecture allows to save up to 10 movements different sequences in the internal memory block. Additionally, it allows modifying any sequence in real time, without affecting the robot operation. The architecture controls 18 servomotors allowing 18 degrees of freedom to the robot. The performing and movement test of the robot are presented.

An Efficient Inverter Logic in Quantum-Dot Cellular Automata for Emerging Nanocircuits

Quantum-dot cellular automata (QCA) has been advocated as one of the most propitious nanoelectronic technologies. The fault rates in QCA are very high due to its susceptibility to cell deposition defects. Also, the power requirements of QCA are getting more critical to avoid either over-design for power rails or unreliability under high-performance stress. Among the different primitive logic structure of QCA, the inverter is keyed out to enable more reliable as well as low-power design. This work proposes a novel approach to generate stimulus for low-power dissipation in QCA logic primitives (inverter) in order to obtain worst-case power scenarios. Hybridizing rotated and non-rotated QCA cell together with a new low-power inverter tile structure in QCA is proposed. Further, the functional characterization of the proposed inverter tile is investigated. Kink energy estimation, as well as simulation results, is considered for verifying the circuit layout and functionality. Moreover, a composable logic block is synthesized that realizes triple fanout (with two inverted output). The reliability of these logic primitives is also extended by implementing full adder and XOR circuit.