Logic Blocks Research Articles

Thermal modelling and layout optimization of GaN half-bridge IC with integrated drivers and power HEMTs

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization.

Analysis of FPGA Architecture with Hybrid Logic Blocks Based on ULG and LUT

This paper analyzes the efficiency of different FPGA architectures consisting of Hybrid logic blocks (HLB) formed with Look-up Tables (LUTs) and Universal Logic Gates (ULGs). Pure LUT-based architectures induce area overhead and a longer delay. A ULG is designed to realize an efficient architecture compared to pure LUT-based architectures. Using this ULG and LUT in different proportions, HLBs are designed. The Field Programmable Gate Array (FPGA) architectures containing these proposed HLB structures are analyzed using various Microelectronics Centre of North Carolina (MCNC) benchmark circuits and compared with the performance of the existing designs. The result shows that the proposed architecture design can save a tremendous amount of time in overall flow and routing along with area improvements.

Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management.

The use of physical unclonable functions (PUFs) linked to the manufacturing process of the electronic devices supporting applications that exchange critical data over the Internet has made these elements essential to guarantee the authenticity of said devices, as well as the confidentiality and integrity of the information they process or transmit. This paper describes the development of a configurable PUF/TRNG module based on ring oscillators (ROs) that takes full advantage of the structure of modern programmable devices offered by Xilinx 7 Series families. The proposed architecture improves the hardware efficiency with two main objectives. On the one hand, we perform an exhaustive statistical characterization of the results derived from the exploitation of RO configurability. On the other hand, we undertake the development of a new version of the module that requires a smaller amount of resources while considerably increasing the number of output bits compared to other proposals previously reported in the literature. The design as a highly parameterized intellectual property (IP) module connectable through a standard interface to a soft- or hard-core general-purpose processor greatly facilitates its integration into embedded solutions while accelerating the validation and characterization of this element on the same electronic device that implements it. The studies carried out reveal adequate values of reliability, uniqueness, and unpredictability when the module acts as a PUF, as well as acceptable levels of randomness and entropy when it acts as a true random number generator (TRNG). They also illustrate the ability to obfuscate and recover identifiers or cryptographic keys of up to 4096 bits using an implementation of the PUF/TRNG module that requires only an array of 4×4 configurable logic blocks (CLBs) to accommodate the RO bank.

FPGA-based Sokuban-like fun logic learning program with combinatorial logic blocks

There are problems such as a high threshold of entry, difficulty understanding the architecture, and boring learning in electronics applications. In order to improve the readability of the structure and learning efficiency, the study proposes a Sokuban-like fun logic learning program based on a Field Programmable Gate Array (FPGA) with combinational logic blocks displayed by VGA. Based on the logic of Sokuban, the program adds "subject", "predicate" and "object" logic blocks, so that the attributes of each object will change with the different combinations of logic blocks. This allows the properties of each object to change with the different combinations of logic blocks, ultimately realizing the process of achieving the same purpose in different ways. The study visualizes the process of writing code by using a specific code framework to transform syntax and entities into different logic blocks that can be changed in different locations. The design solves the problem of the learning process of logical thinking in electronics which is too abstract leading to difficulty in understanding in a relatively easier and more interesting way and can be used as a new way to represent dynamic changes in circuits. In the future, it will not only assist in learning, but can also be used as another new way to represent the output of circuits similar to schematic diagrams, Verilog and other codes, providing a new way of thinking about electronic design.

Design of All-Optical D Flip Flop Memory Unit Based on Photonic Crystal.

This paper proposes a unique configuration for an all-optical D Flip Flop (D-FF) utilizing a quasi-square ring resonator (RR) and T-Splitter, as well as NOT and OR logic gates within a 2-dimensional square lattice photonic crystal (PC) structure. The components realizing the all-optical D-FF comprise of optical waveguides in a 2D square lattice PC of 45 × 23 silicon (Si) rods in a silica (SiO2) substrate. The utilization of these specific materials has facilitated the fabrication process of the design, diverging from alternative approaches that employ an air substrate, a method inherently unattainable in fabrication. The configuration underwent examination and simulation utilizing both plane-wave expansion (PWE) and finite-difference time-domain (FDTD) methodologies. The simulation outcomes demonstrate that the designed waveguides and RR effectively execute the operational principles of the D-FF by guiding light as intended. The suggested configuration holds promise as a logic block within all-optical arithmetic logic units (ALUs) designed for digital computing optical circuits. The design underwent optimization for operation within the C-band spectrum, particularly at 1550 nm. The outcomes reveal a distinct differentiation between logic states '1' and '0', enhancing robust decision-making on the receiver side and minimizing logic errors in the photonic decision circuit. The D-FF displays a contrast ratio (CR) of 4.77 dB, a stabilization time of 0.66 psec, and a footprint of 21 μm × 12 μm.

Fabrication and Characterization of Four-State Inverter Utilizing Quantum Dot Gate Field-Effect Transistors (QDGFETS)

This paper presents the experimental results of nMOS quantum dot gate field-effect transistor (QDG-FET) based four-state inverter fabricated and tested with Si/SiO2 and Ge/GeO2 quantum dots. The site-specific self-assembly of SiOx-cladded Si and GeOx-cladded Ge quantum dot layers in the gate region implements both the driver and load FETs in enhancement nMOS inverters. A four-state inverter will allow the reduction of FET count in logic block in microprocessors.

In-Sensor Tactile Fusion and Logic for Accurate Intention Recognition.

Touch control intention recognition is an important direction for the future development of human-machine interactions (HMIs). However, the implementation of parallel-sensing functional modules generally requires a combination of different logical blocks and control circuits, which results in regional redundancy, redundant data, and low efficiency. Here, a location-and-pressure intelligent tactile sensor (LPI tactile sensor) unprecedentedly combined with sensing, computing, and logic is proposed, enabling efficient and ultrahigh-resolution action-intention interaction. The LPI tactile sensor eliminates the need for data transfer among the functional units through the core integration design of the layered structure. It actuates in-sensor perception through feature transmission, fusion, and differentiation, thereby revolutionizing the traditional von Neumann architecture. While greatly simplifying the data dimensionality, the LPI tactile sensor achieves outstanding resolution sensing in both location (<400µm) and pressure (75Pa). Synchronous feature fusion and decoding support the high-fidelity recognition of action and combinatorial logic intentions. Benefiting from location and pressure synergy, the LPI tactile sensor demonstrates robust privacy as an encrypted password device and interaction intelligence through pressure enhancement. It can recognize continuous touch actions in real time, map real intentions to target events, and promote accurate and efficient intention-driven HMIs.

Accuracy, potential, and limitations of probabilistic record linkage in identifying deaths by gender identity and sexual orientation in the state of Rio De Janeiro, Brazil

BackgroundGlobally, the counting of deaths based on gender identity and sexual orientation has been a challenge for health systems. In most cases, non-governmental organizations have dedicated themselves to this work. Despite these efforts in generating information, the scarcity of official data presents significant limitations in policy formulation and actions guided by population needs. Therefore, this manuscript aims to evaluate the accuracy, potential, and limits of probabilistic data relationships to yield information on deaths according to gender identity and sexual orientation in the State of Rio de Janeiro.MethodsThis study evaluated the accuracy of the probabilistic record linkage to obtain information on deaths according to gender and sexual orientation. Data from two information systems were used from June 15, 2015 to December 31, 2020. We constructed nine probabilistic data relationship strategies and identified the performance and cutoff points of the best strategy.ResultsThe best data blocking strategy was established through logical blocks with the first and last names, birthdate, and mother’s name in the pairing strategy. With a population base of 80,178 records, 1556 deaths were retrieved. With an area under the curve of 0.979, this strategy presented 93.26% accuracy, 98.46% sensitivity, and 90.04% specificity for the cutoff point ≥ 17.9 of the data relationship score. The adoption of the cutoff point optimized the manual review phase, identifying 2259 (90.04%) of the 2509 false pairs and identifying 1532 (98.46%) of the 1556 true pairs.ConclusionWith the identification of possible strategies for determining probabilistic data relationships, the retrieval of information on mortality according to sexual and gender markers has become feasible. Based on information from the daily routine of health services, the formulation of public policies that consider the LGBTQ + population more closely reflects the reality experienced by these population groups.

71‐1: CMOS Backplane Technology and Its Challenge for µLEDoS AR/XR Display

This paper introduces the latest CMOS (Complementary Metal‐Oxide‐Silicon) backplane technology for µLEDoS AR/XR display engines. The backplane supports a display resolution of 1,280RGB x 720 and has been implemented on a 28nm Fully Depleted Silicon on Insular (FD‐SOI) CMOS process in order to meet the requirements such as performance, power, and pixel size. The area of a single pixel is 4.95µm x 4.95µm achieving higher than 5,000 PPI in RGB‐color mode. Each pixel contains 3 independent sub‐pixel drivers and one dependent driver assigned for a red LED. Each sub‐pixel driver includes a 10‐bit video SRAM memory, PWM (Pulse Width Modulation) control logic block, a constant current generator, and LED driver stage to drive red, green, or blue LEDs. The backplane also integrates necessary image processing functions such as De‐mura compensation, dead‐pixel compensation, and digital gamma generation. The top surface of the backplane wafer is also prepared for a wafer‐to‐wafer hybridization bonding between the CMOS wafer and an LED wafer.

Erasable and Field Programmable DNA Circuits Based on Configurable Logic Blocks.

DNA is commonly employed as a substrate for the building of artificial logic networks due to its excellent biocompatibility and programmability. Till now, DNA logic circuits are rapidly evolving to accomplish advanced operations. Nonetheless, nowadays, most DNA circuits remain to be disposable and lack of field programmability and thereby limits their practicability. Herein, inspired by the Configurable Logic Block (CLB), the CLB-based erasable field-programmable DNA circuit that uses clip strands as its operation-controlling signals is presented. It enables users to realize diverse functions with limited hardware. CLB-based basic logic gates (OR and AND) are first constructed and demonstrated their erasability and field programmability. Furthermore, by adding the appropriate operation-controlling strands, multiple rounds of programming are achieved among five different logic operations on a two-layer circuit. Subsequently, a circuit is successfully built to implement two fundamental binary calculators: half-adder and half-subtractor, proving that the design can imitate silicon-based binary circuits. Finally, a comprehensive CLB-based circuit is built that enables multiple rounds of switch among seven different logic operations including half-adding and half-subtracting. Overall, the CLB-based erasable field-programmable circuit immensely enhances their practicability. It is believed that design can be widely used in DNA logic networks due to its efficiency and convenience.

Implementation and Comparison of Wearable Exoskeleton Arm Design with Fuzzy Logic and Machine Learning Control

In this study, a wearable exoskeleton arm was designed and controlled with different control methods to help people with muscle disorders in their arms and support treatment. The developed robot arm was transferred to Simulink software with the Simmechanics application. Two electromyography (EMG) muscle sensors and the ADXL335 position and acceleration sensors attach to the human arm’s biceps and triceps muscle areas. As the human moved the arm, data were obtained from the EMG muscle sensors and the ADXL335 position and acceleration sensor. The received data were first trained with the fuzzy logic algorithm. The same data were then trained with machine learning algorithms in Simulink software. It has been determined that the best result is the quadratic support vector machine (SVM) algorithm. The fuzzy logic algorithm trained with the PID controller block and the received sensor data have been added to the degrees of freedom regions that will enable rotation in the block diagram of the previously exported system. Later, the fuzzy logic block was removed and the machine learning algorithm, the quadratic SVM algorithm, was added. The designed system was operated with two different control systems, and the control algorithm closest to the human arm movement was determined. In addition, each part of the system, whose design was prepared, was removed and assembled separately with a 3D printer. ESP32 microcontroller development board was used to control the system, and it was run in real-time with EMG muscle sensors and position sensors.

Real-Time Hardware Emulation of Microgrid Forming Wireless Power Transfer Systems

The prevalence of wireless charging approaches has manifested a grid-supporting potential which can be evaluated by hardware-based methodologies. In this work, real-time emulation of a bidirectional wireless power transfer (WPT) system capable of DC microgrid formation is investigated on the field-programmable gate array (FPGA). Following a detailed analysis of the transfer characteristics of the dual-active bridge with a series-compensated resonant tank in between, a unified control scheme utilizing a phase-shift strategy is proposed for a flexible voltage or current regulation, thereby enabling the DC microgrid-forming capability. Electromagnetic transient modeling is then carried out so that an accurate digital emulation platform is feasible for prototyping. The fact that the WPT has a high frequency compels a small computation step size, which poses a dramatic challenge to real-time execution. A partition-iteration approach is therefore proposed for matrix dimension reduction which ultimately results in an alleviated processing burden. In the meantime, the parallelism of configurable logic blocks and the pipelined architecture of the FPGA are explored to achieve a low hardware latency. The analytical models, as well as the proposed control method, are validated experimentally, and then real-time hardware emulation of a DC microgrid consisting of WPT systems is performed for an integration study.

Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications

Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is at 40 MHz, which is 92.94% energy reduction compared to its CMOS counterpart. Further, the three proposed adiabatic-logic-based memory cells are 14T, 16T, and 12T designs with at least 88.2%, 84.2%, and 87.2% energy savings. Also, we evaluated the performance of the proposed CLBs using an adiabatic-logic-based LUT (AL-LUT) interfacing with adiabatic-logic-based memory cells. The proposed design shows significant energy reduction compared to a CMOS LUT interface with SRAM cells for different frequencies; the energy savings are at least 91.6% for AL-LUT 14T, 89.7% for AL-LUT 16T, and 91.3% AL-LUT 12T.

Implementation of EnDat Interface Master Using Configurable Logic Block in MCU

In this study, we propose an implementation method of the Encoder Data (EnDat) interface master for slave encoders using only a configurable logic block (CLB) and a serial peripheral interface (SPI) integrated into microcontroller units. By programming the CLB device to execute logic functions and finite state machines designed for the EnDat interface master operation, we realize the EnDat and SPI clocks that are required for the EnDat interface master operation. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are unnecessary for the master implementation. We build a one-axis feed drive system that is powered by an AC motor and equipped with an EnDat linear encoder for measuring table speed and position. By performing various experiments for table position and speed control based on the built feed drive system, we verify the performance and practical usefulness of the implemented EnDat interface master. The maximum EnDat clock frequency without the propagation delay compensation is achieved by 2 MHz, which can cope with 16 kHz control cycle frequency. The usefulness is demonstrated by showing the table speed and position control performance that are acceptable in real applications.

Reduced On-chip Storage of Seeds for Built-in Test Generation

Logic built-in self-test ( LBIST ) approaches use an on-chip logic block for test generation and thus enable in-field testing. Recent reports of silent data corruption underline the importance of in-field testing. In a class of storage-based LBIST approaches, compressed tests are stored on-chip and decompressed by an on-chip decompression logic. The on-chip storage requirements may become a bottleneck when the number of compressed tests is large. In this case, using each compressed test for applying several different tests allows the storage requirements to be reduced. However, producing different tests from each compressed test has a hardware overhead. This article suggests a new on-chip storage scheme for compressed tests that eliminates the additional hardware overhead. Under the new storage scheme, a set of N B -bit compressed tests targeting a set of faults F 0 is translated into a sequence S of N ⋅ B bits. Every B consecutive bits of S are considered as a compressed test. The sequence S thus yields close to N ⋅ B compressed tests, magnifying the test data stored in S almost B times. Taking advantage of the extra tests, the article describes a software procedure that is applied offline to reduce S without losing fault coverage of F 0 . Experimental results for benchmark circuits demonstrate significant reductions in the storage requirements of S and significant increases in the fault coverage of a second set of faults, F 1 .

BLDC Motor Speed Control with Digital Adaptive PID-Fuzzy Controller and Reduced Harmonic Content

Low power brushless direct current (BLDC) motors are used in many consumer appliances. These motors have a relatively high winding resistance and therefore current control loop can be avoided in some cases, but fast and accurate speed regulation can be still needed. To minimize harmonics and generated sound noise, improved sinusoidal pulse width modulation (PWM) has been tested in the paper. As the most suitable commutation type, the sine wave with the third harmonic component has been selected. This type of communication reduced the torque ripple of the motor. This paper analyses the possibility to improve traditional proportional-integral-derivative (PID) speed regulator with Fuzzy logic block. A simulation model of BLDC motor, inverter, speed detection circuit and controller have been created. Simulation results showed that by applying the Fuzzy-based PID controller, the transient time can be reduced from 0.2 s to 0.05 s and overshoot can be avoided in comparison with traditional PID controller. Experimental results show a significant improvement in the motor dynamics—the overshoot and transient time were reduced twice. The difference with simulation results and experimental ones can be explained by delays introduced by the microcontroller.

Design of Reconfigurable Logic Block Based Sequential Circuits Using Look Up Table Logics

Reconfigurable sequential circuits find applications in various digital systems, including communication networks, data processing units, embedded systems, and FPGA-based designs. Their ability to adapt and reconfigure their functionality onthe-fly allows them to accommodate dynamic requirements and optimize the use of hardware resources. Traditional implementations of sequential circuits involve static configurations, where the logic and functionality are fixed during synthesis. While these methods are straightforward to design and implement, they lack adaptability and cannot be modified without redesigning the entire circuit. The proposed method involves the utilization of a dedicated Reconfigurable Logic Block (RLB) within the sequential circuits, allowing for dynamic configuration changes without altering the overall circuit structure. The RLB can be programmed to provide different logic functions using look up tables, multiplexers, enabling the sequential circuit such as counters and shift registers to change its behaviour.

Multidimensional Multi-Connected Fuzzy Interval-Logic Controller

The key features and the principle of operation of a multidimensional fuzzy interval-logic controller with interconnected adjustable parameters developed by the authors are considered. The scheme of interpretation of continuous physical quantities by an equivalent set of terms and the basic version of the block diagram of the regulator are presented. The main elements of the logical output block are described, including the block of production rules, which includes a predefined database of values of control actions on control objects in the form of ordinal numbers of terms of output continuous quantities. The advantages and features of setting up the mutual connections between the input and output continuous values of the regulator are considered, which is expressed in determining the functional dependencies between them. The set of parameters possessed by the terms of input continuous quantities in relation to specific output continuous quantities of the regulator is described. The methods of defuzzification of the values of output continuous quantities within the boundaries of their terms are shown. The possibility of combining input and output continuous quantities into groups when setting up mutual connections between them is described. The mechanism of determining groups of interrelated continuous quantities is illustrated, the total number of which is determined by forming a matrix of relationships, according to the author’s scheme. The algorithm of sequential processing of the contents of the cells of the matrix of relationships, consisting of three steps, is considered. Expressions are given for calculating the basic parameters of a multidimensional fuzzy interval-logic controller with interrelated adjustable parameters. The results of a computational experiment to reduce the system of production rules of the regulator in determining the relationships between input and output continuous quantities are presented.

Využiteľnosť Dienesovho logického bloku v primárnom vzdelávaní

The development of perception is very important for children of younger school age. Primary school teachers can also develop it through manipulation activities. One of the important aids in manipulative activities is also a set of geometric shapes created by the Hungarian mathematician Zoltán Pál Dienes called Dienes' s logical block. The aim of the paper is to bring this tool closer, especially to primary school teachers, and to offer them suggestions of thematic units in which they can use Dienes' logical block.

Sharing of Topped-Off Compressed Test Sets Among Logic Blocks

Sharing of Topped-Off Compressed Test Sets Among Logic Blocks