Local Planarization Research Articles

Analysis of Local Planarization with Polishing Time, Film Thickness, Chemical Non-Uniformity, Line Density, Line Width, and Pad Relaxation Property

AbstractTheoretical chemical mechanical polishing local planarization models as a function of polishing time and film removal are reviewed, and re-derived in a systematic and correlative way. The derived models employ pad viscoelastic and relaxation properties to explain the experimental phenomena that step height local planarization is an exponential function of line width at the same line density, and also account for the affect of pattern density and polishing of two different materials at the same time on step height planarization.

A Microwave High-Density Plasma Source for Submicron Silicon IC Technology

A microwave high-density plasma source is applied for room-temperature deposition of thin SiO2films, filling of submicron trenches, local planarization of the chip surface, etching of deep trenches in the insulator, and resist stripping after ion implantation. The structures obtained meet stringent demands for current technologies. Uniform processing of wafers up to 300 mm in diameter is demonstrated.

Buried word line planarization and roughness control for tunnel junction magnetic random access memory switching

Spin dependent tunnel junctions were fabricated on top of buried word lines. This was achieved modifying an existent 1.2 μm complementary metal–oxide–semiconductor backend metalization process. The word lines are 0.2 μm thick and 4 μm wide. Roughness over the buried line was decreased to 0.2 nm (rms), performing a spin-on-glass local planarization step. Tunnel junctions with 9–13 Å plasma oxidized Al barriers were patterned on top of the word line with different aspect ratios from 3×2 μm2 to 7×1 μm2 areas. Magnetoresistance values reach over 20% for top free electrode configurations. In this inverted structure the magnetization of the free electrode can be fully reversed with the field from word line. The word line creates a field of 0.7 Oe per mA. Applying simultaneously two perpendicular fields reduces the threshold for magnetization switching. The fabricated structure can be used to assess the junction switching mechanism for tunnel junction magnetic random access memories.

Planarization properties of hydrogen silsesquioxane (HSQ) influence on CMP

Low dielectric constant materials are now required as intermetallic dielectrics to reduce RC delay in advanced technologies. Hydrogen silsesquioxane (HSQ) is a spin-on dielectric with a dielectric constant around 3. Local planarization of HSQ and its impact on the global planarization due to CMP process was studied. Local planarization of HSQ and its impact on the global planarization due to CMP process was studied. When lines and spaces are equal, HSQ shows a good planarization for lines smaller than 20 μm. In this case, the HSQ thickness on metal line is equal to 2500 Å, which is the minimum which can be obtained for this metal thickness and HSQ deposited. For various environments of the metal line HSQ planarizes better for small lines in a dense zone created by an array of lines or plates of metal. For the CMP process the planarization is good for small lines, as for HSQ but in an array of lines only. Plates must be totally prohibited for CMP process. Finally, for an intermetal dielectric including HSQ the goal of CMP is no more a local planarization as for gap fill but a large scale intra-die planarization.

A novel sub-half micron Al-Cu via plug interconnect using low dielectric constant material as inter-level dielectric

A novel Al-Cu via plug interconnect using low dielectric constant (low-/spl epsiv/) material as inter-level dielectric (ILD) has been demonstrated. The interconnect structure was fabricated by spin-on deposition of the low-/spl epsiv/ ILD and physical vapor deposition (PVD) of the Al-Cu. Excellent local ILD planarization was achieved by a two-step spin-on coating process. The dielectric constant of the low-/spl epsiv/ no is about 2.7, which leads to significant interconnect wiring capacitance reduction. For the first time, completely filled Al-Cu:0.5% plugs with nearly vertical sidewalls were fabricated in organic low-/spl epsiv/ ILD. Excellent via fill was observed with via size down to 0.30 μm. Low via resistance and excellent via reliability have been observed.

Improved spin‐on glass process with multilevel metallization

AbstractThis paper reports on recent improvements in organic spin‐on glass (SOG) planarization technology combined with etch‐back process. A general rule has been established for SOG planarization mechanism that is suitable for every kind of wiring pattern distribution. This general rule, the volume constant rule, shows that the SOG volume in a certain projection length along the horizontal direction is constant and independent of the wiring width. Based on this rule, it is found that the SOG planarization process margin can be increased significantly by decreasing the plasma SiO2 (= P‐SiO2) layer thickness underneath the SOG layer.The characteristics of this newly developed organic SOG material have been investigated. This new organic SOG material developed by Hitachi Chemical Company, Ltd. (HSG‐2209S‐R7) has heat reflow capability that causes the movement of SOG on the wires to the space during the second baking; this results in improvements in local planarization and decrease in the SOG thickness on the wires.A six‐level metallization test structure for a logic LSI has been successfully created using the optimized process conditions.

Fluorinated interlayer dielectric films in ULSI multilevel interconnections

Fluorinated interlayer dielectric films for ultra large scale integrated circuit (ULSI) multilevel interconnections are investigated. The interlayer dielectric film properties and their formation techniques have to meet three requirements such as: (1) a high planarization capability, (2) a low dielectric constant and (3) a low deposition temperature. To satisfy the three requirements, the technologies such as (i) a fluorinated spin-on-glass (SOG) film by fluorotrialkoxysilane vapor treatment (FAST-SOG), (ii) a fluorinated SiO 2 (SiOF) film by room temperature chemical vapor deposition (RTCVD-SiOF) using fluorotrialkoxysilane (FTAS) and pure water as gas sources, (iii) a room temperature liquid phase deposition (LPD) SiO 2 film, and (iv) fluorinated polyimide siloxane (F-PSI) films are desirable. The RTCVD, FAST and LPD techniques have shown the possibility to reduce the film formation temperature to room temperature by catalytic reactions. The dielectric constant for SiO 2 films can be reduced to 3.7 at 1 MHz by using the RTCVD and LPD techniques. The dielectric constant of 2.7 at 1 MHz can be achieved for the F-PSI films, and is lower than those for conventional polyimide films (3.2–3.5) and SiO 2 films (3.9–4.2). Although the FAST-SOG, RTCVD-SiOF and F-PSI films cannot achieve full planarization, the LPD technique can achieve both global and local planarization because this technique has high capability for selective SiO 2 film deposition. The fluorinated films have other good properties such as low residual stress, low residual OH contents and low moisture absorption, which can enlarge the fabrication margins of multilevel interconnections. These other properties are also very effective for improving the ULSI devices performance.

Fluorinated SiO2 Films For Interlayer Dielectrics In Quarter-Micron Ulsi Multilevel Interconnections

AbstractFluorinated SiO2 films for use as interlayer dielectrics in ULSI multilevel interconnections are investigated. The interlayer dielectric film properties and their formation techniques have to meet the following requirements: (1) a low dielectric constant, (2) a high planarization capability, (3) a high capability for narrow gap filling, and (4) a low deposition temperature for low residual stress. To satisfy these requirements, three technologies have been investigated. They are: (i) a fluorinated SiO2 (SiOF) film by room temperature chemical vapor deposition (RTCVD-SiOF) using fluorotrialkoxysilane (FTAS) and pure water as gas sources, (ii) a room temperature liquid phase deposition (LPD) SiO2 film, and (iii) a fluorinated spin-on-glass (SOG) film by fluorotrialkoxysilane vapor treatment (FAST-SOG). The dielectric constant for SiO2 films can be reduced to 3.7 at 1 MHz by the RTCVD and LPD techniques. Although the FAST and RTCVD techniques cannot achieve full planarization, the LPD technique can achieve both global and local planarization because this technique has high capability for selective SiO2 film deposition. The RTCVD, FAST and LPD techniques have shown the possibility to reduce the film formation temperature to room temperature by catalytic reactions, resulting in low residual stress. Other properties of the RTCVD-SiOF, LPD-SiO2 and FAST-SOG films are good enough for the interlayer dielectric film application. The LPD-SiO2 film shows higher endurance properties to moisture than the RTCVD-SiOF and FAST-SOG films.

Passivation Design / Electromigration Performance Correlations in Layered Aluminum Metallizations

ABSTRACTThe study presented in this paper establishes correlations between key passivation morphological characteristics and metal electromigration performance. This was done by using test structures including extrusion monitors which provided narrow gaps along both sides of the test stripes. The parameters studied were: (1) the nature of the gap filling (oxide process and step coverage), (2) local oxide planarization, and (3) oxide thickness above the leads tested. Failure analysis was conducted by SEM cross-sections of cracked passivation areas. We observed that in the case of aluminum metallizations capped by a thin anti-reflective coating (ARC) layer, failure occurred in all cases by aluminum extrusion from the top corners of the leads, and at 45 degree angles into the passivation. Ultimately, the lifetime was dependent on oxide thickness above the test leads rather than gap-filling characteristics.

Planarization with Cyclotene™ 3022 (BCB) Polymer Coatings

ABSTRACTThis work examines the planarization of polymer thin film coatings derived from Cyclotene™ 3022 prepolymer resins. Cyclotene™ 3022 is a divinyl siloxane bis-benzocyclobutene prepolymer (DVS-BCB, CAS 117732-87-3). It is used primarily as a dielectric in microelectronics applications.Using profilometry, planarization measurements have been made on thin films spun over features consisting of lines and trenches. Feature widths have been varied from 2 to 1000 μm and the feature depths and film thickness have been varied from 1 to 16 μm. Effects of the processing procedure, resin concentration and resin additives have been explored. Local (versus global) planarization will be discussed.Planarization has been found to depend on all feature dimensions and the polymer film thickness. Lines or other structures having a width of 100 μm or less can be planarized to 90% or better with standard commercial formulations of Cyclotene™ 3022, provided that the mean film thickness is twice the line-height or feature-depth. Metals such as Al, Cu, Cr and Ti can all be planarized to this degree; however, surface preparations may influence the result.

Three “Low Dt” Options for Planarizing the Pre‐metal Dielectric on an Advanced Double Poly BiCMOS Process

Three options for planarizing the dielectric separating the polysilicon and first metal in an advanced double poly BiCMOS program are described in terms of both local and long range planarization capabilities. The candidates studied are a sacrificial etchback technique, a high pressure flow of borophosphosilicate glass (BPSG), and a sandwich structure incorporating a spin‐on glass (SOG) layer; these are compared to a conventional BPSG flow process. Local planarization was evaluated by profile angles and metal line resistances on a closely spaced step structure, while the ability to planarize large spaces was measured by a characteristic planarization length. All three techniques offer improved planarity with reduced temperature cycles, but the sacrificial etchback process gives the best values of both local and long range planarization. The high pressure flow excels at local planarization, whereas the SOG sandwich structure yields an intermediate planarization length.

Mechanism for the Local Planarization of Microscopically Rough Surfaces by Drying Thin Films of Spin‐Coated Polymer/Solvent Solutions

When thin films of polymer/solvent solutions are spin coated onto microscopically rough substrates, the dry film profile tends to smooth or planarize those features of the substrate that have lateral dimensions on the order of micrometers and less. A mathematical model is used to explain the physical mechanisms that are responsible for this local planarization. The governing equations are those of conservation of species and overall mass. The finite element method is employed to handle this transient, two‐dimensional, free boundary problem. It is found that local planarization is driven by large lateral concentration gradients that develop during drying, and by the presence before drying of a greater total mass of nonvolatiles per unit area where the film is thicker. The model is applied to isolated grooves and ridges and to a periodic array of grooves/ridges.

Properties of Laser Planarized Aluminum Alloy Films

ABSTRACTAn excimer laser (XeCl, 308 nm) has been used to locally melt and reflow aluminum alloy films into contacts of VLSI device structures resulting in contact filling and local planarization. This technique has the potential to be the answer to the ‘poof’ aluminum step coverage problem. The first order problems are that of ablation and voids. Voids have been categorised as ‘line voids’ and ‘contact voids’. Various processing conditions of the barrier, Al-Si-Cu alloy and Al-Cu alloy metallizations were explored to obtain the optimum process with the desired film characteristics.