Local Oscillator Generation Research Articles

A 54–862-MHz CMOS Transceiver for TV-Band White-Space Device Applications

A 54-862-MHz single-chip CMOS transceiver with a single LC voltage-controlled oscillator (VCO) fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> synthesizer is developed for TV-band white-space communications and cognitive radio applications. The transceiver is based on a single-conversion zero-IF architecture with integrated harmonic filtering capability. A combined harmonic rejection mixer and coarse RF tracking filter significantly lessens the in-band harmonic emission problem in the transmitter, as well as the harmonic mixing problem in the receiver. A fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked loop (PLL) with only a single LC VCO and a wideband multimodulus local oscillator (LO) generator seamlessly covers the entire band. A wideband semi-dynamic divide-by-1.5 circuit is adopted in the LO generator to reduce the VCO tuning range requirement by 25 %. A pseudoexponential capacitor bank structure in the LC VCO substantially reduces the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">step</sub> variations across the total band, which is beneficial for maintaining the PLL loop stability and dynamics over the wide band. The transceiver is implemented in 0.18-μ m CMOS, and operates with a single 1.8-V supply. The transmitter delivers a nominal output power of -3 dBm, and exhibits OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> of >; +6.4 dBm, OIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of >; +15.9 dBm, and error vector magnitude (EVM) of <; -34.7 dB for 64-QAM signal. The image and carrier leakage calibration circuits suppress the leakage components below -41 dBc across the entire band. The receiver achieves about 100-dB gain dynamic range, 3.5-6.9-dB noise figure, <; -29-dB EVM, and -43.4/-59.7-dBc third/fifth harmonic mixing suppression. The synthesizer and LO generator achieves the integrated phase noise <; 0.8 rms degree over the entire band.

SIGE HBT DUAL-CONVERSION WEAVER-HARTLEY DOWNCONVERTERS WITH HIGH IMAGE REJECTION

GHz dual-band Weaver-Hartley dual-conversion downconverters are demonstrated using 0.35-m SiGe heterojunction bipolar transistor (HBT) technology with/without a correlated local oscillator (LO) generator. In the flrst implementation, the correlated LO generator consists of a divide-by-two frequency divider, a frequency doubler and a single-sideband upconverter and thus LO1 (= 2:5£LO2) signal is generated. As a result, the downconverter with the correlated LO signals has image-rejection ratios of more than 39dB for the flrst/second image signals (IRR1/IRR2) of the dual-conversion system at both 2.4/5.7-GHz modes while the downconverter without the correlated LO generators has a 6-dB higher conversion gain and IRR1/IRR2 of more than 44dB with the same dc power consumption (excluding the LO generator). On the other hand, a 10-GHz Weaver- Hartley downconverter is demonstrated with a resonant LC load at the flrst-stage mixer to improve the conversion gain at high frequencies. The downconverter achieves a conversion gain of 8dB with IRR1/IRR2 better than 43/40dB.

고속 표적 추적을 위한 K-대역 레이다 송수신기 설계

This study is to design FMCW radar transceiver of K-band which is used to detect and track approaching high speed targets with low altitude. The transmitter needs high output power due to small RCS targets and wide beamwidth of transmit antenna. Multi-channel receivers are required to detect and track targets by interferometer method. Transmitter consists of high power amplifier, waveguide switch, and frequency up-converter. Receiver is composed of five channel receivers, up and down converters, X-band local oscillator and waveform generator. Before manufacturing it, the proposed architecture of transceiver is proved by modeling and simulation using several parameters. Then, it is manufactured by using industrial RF components. The performance parameters are measured through experiment. In the experiment, transmitting power and receiver gain were measured with 39.64 dBm and 29.1 dB, respectively. All other parameters in the specification were satisfied as well.

Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications

Multiphase local-oscillator (LO) generators have been widely adopted in modern wireless communication systems. This paper describes the analysis and design of two open-loop multiphase (quadri and octave) LO generators, which can lead to speed relaxation of the phase-locked loop and voltage-controlled oscillator when compared with conventional frequency-division methods. The mathematical model, sizing considerations, and two design examples targeting mobile-TV applications are presented. The first one is an octave-phase LO generator designed in 90-nm CMOS featuring multiple switchable phase correctors in cascade. It covers the VHF-III and UHF bands with an optimized phase precision within 0.8° . The second one combines quadri- and octave-phase LO generation to cover the full band of mobile TV from 170 to 1700 MHz. Optimized in 65-nm CMOS, it can be operated in octave-phase mode for image-reject harmonic-reject downconversion or in quadri-phase mode for simple image-reject downconversion. Extensive simulations accounting for process variations show that the achieved phase precisions are within 1.5° (quadri) and 1° (octave). The phase-noise performance is comparable with state-of-the-art solutions.

Design of SIPC‐based complementary LC‐QVCO in 0.18‐μm CMOS technology for WiMAX application

PurposeThe purpose of this paper is to design and realize a low‐phase noise, high‐output power, and high‐tuning range, fully integrated source injection parallel coupled (SIPC)‐based inductor‐capacitor (LC)‐quadrature voltage controlled oscillator (QVCO) covering WiMAX frequency range in 0.18‐μm deep submicron CMOS technology.Design/methodology/approachA pMOS based‐SIPC LC‐QVCO topology is realized with the center frequency of 2.58 GHz. On chip spiral inductor is integrated with substantial quality factor, Q coupled with underlying pattern ground shield (PGS) shielding. An enhanced tuning range is achieved by integrating the diode connected MOS‐based varactors. The CMOS‐based autonomous SIPC LC‐QVCO circuit was characterized for its output phase noise, tuning range and power spectrum response via wafer probing, utilizing a signal source analyzer (Agilent E5052 A).FindingsA quadrature oscillator catering to the needs of local oscillator (LO) generation covering the frequency range of WiMAX is realized. The parallel coupled architecture adapts direct source coupling, bypassing the LC resonator tank and relaxes the close in phase noise up‐conversion. The design consumes 2.19 mm2 of active chip area and measures a phase noise of −114.34 dBc/Hz at 1 MHz of offset frequency with 2.67 GHz of output frequency at 0.9 V of input tuning voltage. The corresponding output power measures to be −10.1 dBm, well suited for mixer hard switching. The design is realized in one poly, six metal 0.18‐μm standard CMOS technology.Research limitations/implicationsOwing to convergence discrepancy in the analysis, a diode‐connected MOS varactor is adapted in contrary to the accumulation mode MOS varactors with superior tuning range.Practical implicationsThe designed SIPC LC‐QVCO is of need in the generation of low‐phase noise, highly matched quadrature LO generation covering the WiMAX frequency range. The adapted parallel coupling also relaxes the voltage headroom limitation.Originality/valueThis paper shows how a fully integrated CMOS‐based SIPC LC‐QVCO architecture is adapted with low‐output phase noise and low voltage headroom consumption covering the WiMAX frequency range.

Passive optical interferometer without spatial overlap between the local oscillator and signal generation

A passively stabilized third-order optical interferometer that spatially separates the local oscillator and signal generation is demonstrated with long-term phase stability. The lack of spatial overlap eliminates unwanted contamination of either field. Fully independent optical control over both fields is exerted after the sample. This independence is taken advantage of with what we believe to be a new approach to scanning the relative phase between the local oscillator and signal that has very high precision and reproducibility. The independence of the fields is also exploited in a flexible balanced heterodyne detection scheme.

Generation and Transmission of Optical Carrier Suppressed-Optical Differential (Quadrature) Phase-Shift Keying (OCS-OD(Q)PSK) Signals in Radio Over Fiber Systems

We propose and experimentally demonstrate generation of optical carrier suppressed-optical differential phase-shift keying (OCS-oDPSK) modulation format in radio-over-fiber (RoF) systems using one single-drive Mach-Zehnder modulator (MZM). This scheme realizes up-conversion of baseband data for downlink wireless service delivery, generation of remote local oscillator (LO) signal for down-conversion of uplink radio frequency (RF) signal, and remodulation of down-converted uplink data, thus lowering the cost of base stations (BSs) in full-duplex RoF systems. The proposed scheme is expected to be simple and compact due to the use of a single MZM. Furthermore, the OCS-oDPSK generation principle is extended to obtain an OCS-optical differential quadrature phase-shift keying (OCS-oDQPSK) signal by employing a dual-parallel MZM (DPMZM), which is useful to deliver multiple wireless services on the same RF carrier.

Self-Coherent Multisymbol Detection of Optical Differential Phase-Shift Keying

This paper treats the recently emerging self-coherent multisymbol decision-feedback-aided detection techniques for optical differential phase-shift keyed (DPSK) transmission based on both an optical preprocessing approach and an electronic postprocessing approach. We present in detail i) the generation of a synthetic low phase-noise effective local oscillator out of the modulated optical data itself, and its estimation theory interpretation; ii) the role of polyphase (interleaved) DPSK in the optical preprocessing approach in easing the decision feedback realization requirements; iii) detection of M-ary DPSK modulation formats for general M, and differential quadrature phase-shift keying in particular; iv) three alternative integrated-optoelectronic receiver implementations for the optical preprocessing approach detailing the structures of the interferometric front-end and the high-speed electronic analog and digital building blocks; and v) the principle, and alternative implementations, of the digital postprocessing approach to self-coherent detection. We finally compare the capabilities of the emerging self-coherent detection and digital coherent detection techniques.

Current Reusing VCO and Divide-by-Two Frequency Divider for Quadrature LO Generation

For low-power and accurate quadrature local oscillator (LO) signal generation, an LC-tank voltage controlled oscillator (VCO) operating at double the required LO-frequency reuses the bias current of divide-by-two frequency divider. The current reusing VCO and divide-by-two frequency divider are targeted to generate the LO signals for a 1.57 GHz global positioning system receiver. Implemented in a 0.18 mum CMOS technology, the current reusing VCO and divide-by-two frequency divider consumes 1.7mA from a 1.8 V supply. The measured phase noise is -120dBc/Hz at 1 MHz offset when the carrier frequency is 1.57GHz.

A 24-GHz Receiver Frontend With an LO Signal Generator in 0.18-$\mu$m CMOS

Utilizing a standard 0.18-mum CMOS process, a receiver frontend and a local oscillator (LO) module are implemented for RF applications at the 24-GHz industrial, scientific, medical band. The proposed frontend is composed of a three-stage low-noise amplifier, a down-conversion mixer, and IF amplifiers. With an IF frequency of 4.82 GHz, the fabricated circuit demonstrates a conversion gain of 28.4 dB and a noise figure of 6.0 dB while maintaining an input return loss better than 14 dB. The measured P in - 1dB and IIP3 of the receiver frontend are -23.2 and -13.0 dBm, respectively. In addition, a circuit module, which generates the required dual down-conversion LO signals, is also included in this study. The proposed LO generator consists of a 19-GHz low-phase-noise voltage-controlled oscillator (VCO), a 4 : 1 frequency divider, and a quadrature phase-tuning circuit. From the measurement results, the VCO exhibits a tuning range of 850 MHz and a phase noise of -110 dBc/Hz at 1-MHz offset frequency. Operated at a supply voltage of 1.8 V, the current consumptions for the receiver frontend and the LO generator are both 30 mA.

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1-5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mum CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.

CMOS balanced regenerative frequency dividers for wide-band quadrature LO generation

CMOS regenerative frequency dividers, based on a fully balanced Gilbert cell, are analyzed in this paper for quadrature local oscillator (LO) signal generation. Driven in opposite phase by double frequency signals, they provide quadrature waveforms while simultaneously driving large mixers LO input capacitances, thereby avoiding power hungry buffers typically required. Experimental results, carried out on 0.18μm CMOS prototypes, show 68% bandwidth around 2GHz center frequency, with a quadrature accuracy better than 1°, making them suitable for multi-standard wireless receivers. To keep the output amplitude constant while simultaneously minimizing the average power consumption, a digital calibration loop regulates each divider biasing current.

A dual-b and RF front-end of direct conversion receiver for wireless CDMA cellular phones with GPS capability

A highly integrated direct conversion receiver for cellular code division multiple access (CDMA) and GPS applications is successfully developed using a 0.5-/spl mu/m SiGe BiCMOS technology. The receiver consists of two low-noise amplifiers (LNAs), a dual-band mixer, two voltage-controlled oscillators (VCOs), a local-oscillator signal generation block, and channel filters. The CDMA LNA achieves a noise figure of 1.3 dB, an input-referred third-order intercept point (IIP3) of 10.9 dBm, and a gain of 15.3 dB with a current consumption of 9.8 mA in the high-gain mode. The mixer for the CDMA mode achieves an uncalibrated input-referred second-order intercept point of 53.7 dBm, an IIP3 of 6.4 dBm, a noise figure of 7.2 dB and a voltage gain of 37.2 dB. The phase noise of the CDMA VCO is approximately -133 dBc/Hz at a 900-kHz offset from a 1.762-GHz operating frequency. It exceeds all the CDMA requirements when tested on a handset.

Bidirectional radio-over-fiber link employing optical frequency multiplication

We propose a bidirectional radio-over-fiber link consisting of an optical downlink transmission employing the optical frequency multiplication principle, a remote local oscillator (LO) generation, a remote down-conversion of the radio-frequency uplink signals, and an optical uplink transmission employing intensity modulation-direct detection. Experiments demonstrate the optical up-conversion of 64-level quadrature amplitude modulated radio signals to 17.8 GHz after transmission over 4.4 km of multimode fiber, 12.5 and 25 km of single-mode fiber in the downlink; the uplink performance is evaluated in terms of down-conversion loss employing the optically generated LO.

Time jitter analysis of 1-bit sigma-delta synthesizer

This letter presents a general analysis of time jitter in sigma-delta synthesizer. One of the practical applications of 1-bit sigma-delta systems is a generation of high-resolution local oscillator (LO) signals. In order to generate LO signals, one may use a single-bit sigma-delta technique to encode sine waves. Today, direct generation of high-frequency sine wave using a clock with higher frequency, is possible. In this letter, we will analyze different LO signal generators and develop a practical way of computation to decide how to choose the best configuration under minimum degradation of signal-to-noise ratio (SNR) at the output.

A Dual-Mode 2.4-GHz CMOS Transceiver for High-Rate Bluetooth Systems

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-on-chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on-chip filters. The chip is fabricated on a 6.5-mm2 die using a standard 0.25-μm CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of −5 dBm, and a sensitivity of −77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4-diffrential quadrature phase-shift keying (π/4-DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver

Subharmonically pumped frequency down- and upconversion circuits are implemented in 0.18-/spl mu/m mixed-mode CMOS technology for 2-GHz direct-conversion WCDMA transceiver applications. These circuits operate in quadrature double-balanced mode and a required octet-phases (0/spl deg/, 45/spl deg/, 90/spl deg/, 135/spl deg/, 180/spl deg/, 225/spl deg/, 270/spl deg/, and 315/spl deg/) local oscillator (LO) signal comes from an active multiphases LO generator composed of a polyphase filter and active 45/spl deg/ phase shifting circuits. For linearity improvement, predistortion compensation and negative feedback schemes are used in the frequency down- and upconversion circuits, respectively. The downconverter achieves a conversion voltage gain of 20 dB (to 1-M/spl Omega/ load), 4-dBm IIP3 (18-dBm OIP3 to 50-/spl Omega/ load), 41-dBm IIP2 and 8.5-dB DSB NF at 1-MHz IF frequency, consuming 13.4 mA from 1.8-V supply, in the WCDMA Rx band (2110-2170 MHz). The upconverter, operating as two switched gain modes in the WCDMA Tx band (1920-1980 MHz), consumes 19.4 mA from 1.8-V supply and shows 14.5-dB conversion power gain, 15 -dBm OIP3 (0.5-dBm IIP3) and -11 dBm P/sub 1dB/ at maximum gain mode. At minimum gain mode, it realizes -0.3-dB conversion loss, 10.7-dBm OIP3 (11-dBm IIP3) and 0-dBm P/sub 1dB/, respectively. 3GPP WCDMA modulation tests are performed for both up- and downconversion circuits and the results are discussed in this paper.

A Fully Integrated 0.18-&amp;gt;tex&amp;lt;$mu$&amp;gt;/tex&amp;lt;m CMOS Direct Conversion Receiver Front-End With On-Chip LO for UMTS

This paper presents a 0.18-/spl mu/m CMOS direct-conversion IC realized for the Universal Mobile Telecommunication System (UMTS). The chip comprises a variable gain low-noise amplifier, quadrature mixers, variable gain amplifiers, and local oscillator generation circuits. The solution is based on very high dynamic range front-end blocks, a low-power superharmonic injection-locking technique for quadrature generation and continuous-time dc offset removal. Measured performances are an overall gain variable between 21 and 47 dB, 5.6 dB noise figure, -2 dBm out-of-band IIP3, -10 dBm in-band IIP3, 44.8-dBm minimum IIP2, and -155-dBc/Hz phase noise at 135 MHz from carrier frequency, while drawing 21 mA from a 1.8-V supply.

Calibration techniques of active BiCMOS mixers

This paper describes calibration techniques for downconversion mixers used in integrated direct-conversion receivers. A method of achieving a high even-order intermodulation rejection is presented. Using the method presented, the receiver second-order input intercept point (IIP2) can always be improved by more than 20 dB. The minimum achieved receiver IIP2 after calibration is +38 dBm. A technique to enhance the I/Q-amplitude balance between the quadrature channels is also introduced. A single-balanced adjustable mixer is implemented as a part of a prototype direct-conversion receiver. The receiver chip consists of a low-noise amplifier, mixers and calibration circuitry, a divide-by-two circuit, local oscillator (LO) buffers for LO generation, and active baseband filters. The chip is fabricated using a 0.35-/spl mu/m SiGe BiCMOS process and is characterized at 900 MHz.

Fully integrated W-CDMA IF receiver and IF transmitter including IF synthesizer and on-chip VCO for UMTS mobiles

A fully integrated, dual intermediate frequency (IF) receiver and an IF transmitter, each with on-chip IF synthesizer, for use in third-generation wide-band code division multiple access (W-CDMA) mobiles has been implemented in a standard, high-frequency, Si-bipolar process with an f/sub T/ of 25 GHz. The IF receiver (318 MHz) and IF transmitter (285 MHz) include a complete phase-locked loop (PLL) and on-chip voltage-controlled oscillator (VCO) with integrated varactors and transformers. The VCOs are used for on-chip local oscillator (LO) generation and operate at four times IF, 1272 MHz and 1140 MHz, for Rx and Tx, respectively. Fully integrated, active, analog base-band filters further increase functionality and integration level. In the receiver, a channel select filter, composed of a fifth-order Chebyshev lowpass filter and a first-order all-pass filter, is implemented. In the transmitter, a fifth-order Butterworth low-pass filter functions as a reconstruction filter. Both devices operate on 2.7-3.3-V supply. The designs comply with ARIB W-CDMA and UMTS standards. Each chip is mounted in a small outline, 32-pin, leadless surface mount package.