A Dual-Mode 2.4-GHz CMOS Transceiver for High-Rate Bluetooth Systems

Abstract

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-on-chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on-chip filters. The chip is fabricated on a 6.5-mm2 die using a standard 0.25-μm CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of −5 dBm, and a sensitivity of −77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4-diffrential quadrature phase-shift keying (π/4-DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.