Local Interconnect Research Articles

Altered Brain Network Segregation in Fragile X Syndrome Revealed by Structural Connectomics.

Fragile X syndrome (FXS), the most common inherited cause of intellectual disability and autism spectrum disorder, is associated with significant behavioral, social, and neurocognitive deficits. Understanding structural brain network topology in FXS provides an important link between neurobiological and behavioral/cognitive symptoms of this disorder. We investigated the connectome via whole-brain structural networks created from group-level morphological correlations. Participants included 100 individuals: 50 with FXS and 50 with typical development, age 11-23 years. Results indicated alterations in topological properties of structural brain networks in individuals with FXS. Significantly reduced small-world index indicates a shift in the balance between network segregation and integration and significantly reduced clustering coefficient suggests that reduced local segregation shifted this balance. Caudate and amygdala were less interactive in the FXS network further highlighting the importance of subcortical region alterations in the neurobiological signature of FXS. Modularity analysis indicates that FXS and typically developing groups' networks decompose into different sets of interconnected sub networks, potentially indicative of aberrant local interconnectivity in individuals with FXS. These findings advance our understanding of the effects of fragile X mental retardation protein on large-scale brain networks and could be used to develop a connectome-level biological signature for FXS.

Temperature-Dependent Comparison Between Delay of CNT and Copper Interconnects

The performance of gigascale integration chips improves by cryogenic technologies such as subambient cooling. In these conditions, interconnects may perform at temperatures as low as 50 K. However, the local temperature of interconnects could easily be as high as 600 K at high-temperature chips. In this brief, we investigated the impact of temperature on delay of local, intermediate, and global interconnects of International Technology Roadmap for Semiconductors Node 2024. This is done for different values of interconnect width and length, nanotube diameter, and percentage of metallic carbon nanotubes (CNTs) in a grown bundle. Results are compared with those of copper counterpart. We showed that for local layers, a bundle of single-walled CNTs (BSWNTs) interconnects could outperform copper interconnects up to 17%, 35%, and 44%, respectively, at 50, 300, and 600 K, whereas for intermediate and global layers, there is a negligible difference between delay of copper and BSWNT interconnects at all temperatures.

Analysis of temperature dependent power supply voltage drop in graphene nanoribbon and Cu based power interconnects

In this paper, we propose a temperature dependent resistive model of multi layered graphene nanoribbon (MLGNR) and Cu based power interconnects. Using the proposed model, power supply voltage drop (IR-drop) analysis for 16 nm technology node is performed. The novelty in our work is that this is the first time a temperature dependent IR-Drop model for MLGNR and Cu interconnects is proposed. For a temperature range from 150 K to 450 K, the variation of resistance of MLGNR interconnect is ~2–5× times lesser than that of traditional copper based power interconnects. Our analysis shows that MLGNR based power interconnects can achieve ~1.5–3.5× reduction in IR-drop and ~1.5–3× reduction in propagation delay as compared with copper based interconnects for local, intermediate and global interconnects.

Temperature Dependent IR-Drop Analysis in Graphene Nanoribbon Based Power Interconnect

The paper proposes a temperature dependent resistive model of graphene nanoribbon (GNR) based power interconnects. Using the proposed model, IR-drop analysis for 16nm technology node latest by ITRS is performed. For a temperature range from 150 K to 450 K, the variation of resistance of GNR interconnect is ~ 2-5  times lesser than that of traditional copper based power interconnects. Our analysis shows that GNR based power interconnects can show ~ 2-3 times reduction in Peak IR-drop as compared with copper based interconnects for local, intermediate and global interconnects.

Breakdown current density in h-BN-capped quasi-1D TaSe3 metallic nanowires: prospects of interconnect applications.

We report on the current-carrying capacity of the nanowires made from the quasi-1D van der Waals metal tantalum triselenide capped with quasi-2D boron nitride. The chemical vapor transport method followed by chemical and mechanical exfoliation were used to fabricate the mm-long TaSe3 wires with the lateral dimensions in the 20 to 70 nm range. Electrical measurements establish that the TaSe3/h-BN nanowire heterostructures have a breakdown current density exceeding 10 MA cm(-2)-an order-of-magnitude higher than that for copper. Some devices exhibited an intriguing step-like breakdown, which can be explained by the atomic thread bundle structure of the nanowires. The quasi-1D single crystal nature of TaSe3 results in a low surface roughness and in the absence of the grain boundaries. These features can potentially enable the downscaling of the nanowires to lateral dimensions in a few-nm range. Our results suggest that quasi-1D van der Waals metals have potential for applications in the ultimately downscaled local interconnects.

Performance Improvement in SC-MLGNRs Interconnects Using Interlayer Dielectric Insertion

Due to their higher resistance, single layer graphene nanoribbons (GNRs) are not suitable for high-speed on-chip interconnect applications. Hence, we use multilayer GNRs (MLGNRs) that offer multiple conduction channels and lower resistance. However, MLGNRs turn into graphite as the number of layers increase, which reduces the mean-free path of each layer. Insertion of a dielectric between GNR layers prevents its conversion into graphite, thereby improving its mean-free path and scattering rate. In this paper, we are proposing an analytical model for the time-domain analysis of side-contact MLGNRs (SC-MLGNRs) with intermediate dielectric insertion. The proposed model computes scattering rate, mean-free path, and carrier mobility in GNRs where dielectric has been inserted between individual layers. Our analytical results for mobility and scattering rate have been verified with the existing experimental data that exhibit excellent accuracy (maximum of error 4% for mobility and 16% for scattering time). Based on our analysis, we have found that the electron mean-free path in GNRs strongly depends on surrounding dielectric environment. In that, the mean-free path increases with interlayer insertion of high- $k$ dielectrics. Equivalent $RLC$ parameters, delay, energy-delay product, and bandwidth density are calculated for our proposed GNR interconnects using our model. We observe that these performance metrics significantly improve due to the presence of dielectric between GNR layers. When compared with Cu interconnects, insertion of HfO2 between GNR layers results in reduction in both propagation delay and energy-delay product by $2\times $ for interconnect lengths of $1400 ~\mu \text{m}$ . In addition, zigzag SC-MLGNR interconnect with $N=10$ and $\varepsilon _{2}=20$ gives nearly 35% higher bandwidth density than that of Cu interconnects for all interconnect lengths. In our analysis, we propose a new performance metric, bandwidth density/energy-delay product to determine the performance limits of our proposed interconnect structure. Finally, we compare the performance of SC-MLGNR interconnect structure with copper and optical interconnects to exhibit its application in local and global interconnects.

On Temperature Dependency of Delay for Local,Intermediate, and Repeater Inserted Global Copper Interconnects

Cryogenic technologies not only improve the performance of interconnects but also the performance of transistors and consequently drivers and repeaters. Although in cryogenically cooled integrated circuits the local temperature of interconnects and transistors may be as low as 50 K, it may easily reach to 600 K in high-temperature chips. In this brief, we investigated the impact of temperature on the delay of local, intermediate, unit-repeater-inserted (URI), and cascaded repeater-inserted (CRI) global copper interconnects for minimum technology node with available transistor model (32-nm technology). Our results show that temperature variation of driver resistance could change the delay of local and intermediate interconnects, respectively, down to −33% and −28% at low temperatures, and up to +240% and 232% at high temperatures relative to the room temperature delay. Moreover, while the contribution of temperature dependency of interconnect is negligible for local and intermediate layers, the temperature dependency of repeater and interconnect could vary the delay of URI and CRI global layer interconnect down to −23% and −38% at low temperatures, and up to +116% and +200% at high temperatures, respectively.

Reconstructing dynamical models from optogenetic data

Optogenetics allows optical control of neuronal activity by using genetically altered neural cells and optical tools. Briefly, optogenetics uses a photosensitive element that, upon absorption of light, produces some change in the activity of the cells. Although the technique evolved, it involves inserting a light-sensitive channel from green algae, called channelrhodopsin-2 (ChR2), into neurons [1]. By precise spatial and temporal delivery of light pulses we can identify the local interconnections among neurons and investigate their dynamical response under different conditions. Data were recorded with a custom made optrode made of a recording pipette glued to optic fiber inserted in the medial prefrontal cortex (PFC) of male PV-Cre mice injected with virus suspension AV2/5.EF1a.DIO.hChR2(H134R)-EYFP.WPRE.hGH [2]. A 473 nm laser generated light stimulation and stable single unit recordings were monitored before filtering to record field potentials (0.1-100 Hz). Optical stimulation consisted of 10 ms pulses followed by 15 ms pause (40 Hz). A train of 10 pulses that lasted 250 ms was applied every 4 seconds and local filed potentials were recorded with a sampling rate of 10 KHz (Figure ​(Figure1A).1A). We used delay-embedding method to reconstruct the phase space attractor [3]. We found that the minimum dimension that unfolds the attractors is three and the delay time is about 3600 data points (Figure ​(Figure1B).1B). Based on the phase space reconstruction, we were able to extract a low-dimensional mathematical model that describes the dynamics of the system. Although every single neuron in the mPFC is described by a large number of independent variables such as ionic channel activation/inactivation variables, the local neural network activated by light pulses can be modeled with only three variables. We hypothesize these three global variables could be the activity of excitatory, inhibitory interneurons, and light-sensitive neurons. Figure 1 A. Average local filed potential (LFP) recordings that show the response of mPFC to 250 ms light stimuli. B. Phase space reconstruction of LFP using delayed embedding method in a three dimensional space and a delay time of 3600 data points (360 ms).

Design of n-Tier Multilevel Interconnect Architectures by Using Carbon Nanotube Interconnects

In this paper, n-tier methodology is developed to design multilevel interconnect architecture of macrocells using single-wall carbon nanotube (SWCNT) bundles. Upper limit of low-bias voltage of SWCNT bundle interconnects is derived and its dependence on temperature, SWCNTs’ diameter, and interconnect length is studied. Possibility of using SWCNT bundles as local interconnects at 7.5-nm technology node is discussed, and it is shown that SWCNT bundles with 1 nm diameter cannot be used at the first interconnect metal level. Using Cu and SWCNT bundles, multilevel interconnect architecture of a 7.5-nm ASIC macrocell is designed which reduces the number of metal levels by 27% and power dissipation by 25% compared with the multilevel interconnect architecture designed with only Cu. The effect of aspect ratio (AR) on the n-tier design is studied. It is shown that decreasing AR of SWCNT bundle interconnects, decreases total power dissipation of the ASIC macrocell by 41%. The impact of temperature variation on the design of multilevel interconnect architecture is also investigated.

Comparison between e-beam direct write and immersion lithography for 20-nm node

E-beam direct write (EBDW) process window (PW) simulations were performed on critical layers in Altera designs of the 20-nm node (minimum metal half-pitch 32 nm). For selected layout clips, a direct comparison is made with 193i simulation results. Local interconnect and Via0 (single patterning) and Metal1 (litho-etch-litho-etch double patterning) layers are considered. The EBDW dose latitude was found to exceed that of the 193i process by a factor of 4. As the electron beam total spot size is of the order of the critical dimension for the considered node, interplay between neighboring features is low. This results in straightforward data preparation with typically two kernels and “clean” PWs. The latter are mainly limited by edge placement errors of line ends. The curves for the various simulation sites roughly overlap, as opposed to the 193i case in which they significantly differ. In EBDW, the performance of square vias equals that of rectangular vias, enabling a denser via packing.

Modeling of Resistance in FinFET Local Interconnect

We present an innovative and comprehensive approach to model the resistance of local interconnect used in FinFET technologies. Our parasitic resistance formulas for FinFET source/drain regions cover both merged and unmerged fin processes. Both simple and composite local interconnect cases are studied. They have been verified with field solver simulation results, and are found to be accurate over a wide range of parameter values. Our local interconnect resistance model has been used in IBM 14 nm SOI FinFET CMOS technology, and is a critical part of compact models used in both extraction flow and schematic/pre-layout flow.

Reactive Power Compensation in Oman 400kV Transmission System

The objective of this paper is to present the challenges, methodological approach and possible solutions for the overvoltage issue during the winter light load period in the Main Interconnected Transmission System (MITS) of Oman after introducing the new 400kV system. Load flow studies of the planned MITS in 2016, including representation of other local and GCC interconnection grids, have shown overvoltage issues at the 400kV substations in Oman during winter off-peak demand. These voltage issues can even lead to difficulties in synchronizing the 400kV circuits. Simulation results are presented to define the size and location of a reactive power compensator which can resolve such overvoltage issues. Many options of the reactive power compensation, including fixed and variable means, have been studied and the best option (fixed shunt reactors) is selected.

(Invited) Ultralow-Voltage Design and Technology of Silicon-on Thin-Buried-Oxide (SOTB) CMOS for High Energy Efficient Electronics in IoT Era

Highly energy efficient CMOS circuits are required in theinternet-of-things (IoT) era since a great number of smallelectronic apparatuses process and communicate data. Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy (Emin) point (MEP) is effective, most of the scaled circuits operate with far higher energy than Emin. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control.[1,2] These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. The MEP operation is generally very slow, e.g. less than 1MHz. The variable Vth approach with adaptive back-bias control can mitigate the situation of decreasing energy as low as possible down to MEP while satisfying the required frequency. Another obstacle is the variability of transistors, which degrades operation margin especially at low Vdd. To solve these problems, we are developing silicon on thin buried oxide (SOTB) [3-4]. In this paper, we demonstrate SOTB’s small variability, back-bias control, and ULV circuit operation. SOTB Device Results A cross-section of the SOTB/bulk hybrid CMOS and a TEMphoto are shown in Figs. 1 and 2. The back-bias voltages, Vbn and Vbp, are applied to the well regions below BOX. The local interconnect by the silicide at the well contact region contributes to improving the back-bias voltage stability. Details of the SOTB process and electrical characteristics are described in [3]. Very small Vth and Ion variability was demonstrated [3] for one million transistors The Pelgrom coefficient was ~1.3 mVμm, the smallest level taking the gate-oxidethickness (Tinv = 2.4 nm) into account. With this improvement, we confirmed 6-T SRAM operation (2 Mbit) at less than 0.4 V (Fig.3 (a)) with a 5.5-ps access time and demonstrated that the minimum operating voltage can be controlled at <0.4 V across whole 300mmF wafer (Fig.3 (b)). The back bias control successfully reduced the standby leakage of SRAM to 0.4pA/cell, which meet the requirement of IoT application (Fig.4). Furthermore, we demonstrated the compensation of temperature change or global variability by back bias control [3-4], resulting further improvement of operation margin at low Vdd. SOTB Circuit Design and ULV Operation We developed a standard cell library for the SOTB technology. The SOTB design flow is basically the same as that for the bulk technology. Using our SOTB flow, various logic circuits were designed and ULP operations were confirmed, such as an accelerator [5] and flex-power FPGA with back biasing [6]. We designed a micro-controller chip dedicated to the sensor-node application [7]. This chip operated at Vdd = 0.35 V and consumed only E = 13.4 pJ. The sleep current was only 0.14 μA. We demonstrated sensor-node operation. The CPU was operated with a single PV cell at <0.4 V. Temperature and acceleration were monitored, and only in an emergency (health problems), an alert was sent via Bluetooth low energy (BLE) to a tablet. Acknowledgment This work was performed as “Ultra-Low Voltage Device Project" funded and supported by METI and NEDO.

Is the brain really a small-world network?

It is commonly assumed that the brain is a small-world network (e.g., Sporns and Honey 2006). Indeed, one of the present authors claimed as much 15 years ago (Hilgetag et al. 2000). The small-worldness is believed to be a crucial aspect of efficient brain organization that confers significant advantages in signal processing (e.g., LagoFernandez et al. 2000). Correspondingly, the small-world organization is deemed essential for healthy brain function, as alterations of small-world features are observed in patient groups with Alzheimer’s disease (Stam et al. 2007), autism (Barttfeld et al. 2011) or schizophrenia spectrum diseases (Liu et al. 2008; Wang et al. 2012; Zalesky et al. 2011). While the colloquial idea of a small, interconnected world has a long tradition (e.g., Klemperer 1938), the present concept of small-world features of networks is frequently associated with the Milgram experiment (Milgram 1967) that demonstrated surprisingly short paths across social networks (‘six degrees of separation’). The concept was formalized by Watts and Strogatz (1998), who derived small-world networks from regular networks by including a small proportion of random network shortcuts. Such an organization results in short paths across the whole network—almost as small as in random networks—combined with local ‘cliquishness’ (or clustering) of neighboring nodes, due to dense local interconnections. These features can be mathematically summarized by the smallworld coefficient (Humphries et al. 2006), which is defined as the clustering coefficient of a given network (normalized by the clustering coefficient of a same-size random network) divided by the network’s normalized average shortest pathlength. While any network that has a smallworld coefficient larger than one is formally a small-world network, for many researchers, the term has become associated with the specific Watts and Strogatz model that is based on the partial random rewiring of a regular network (Fig. 1a). Indeed, the estimation of the rewiring probability has been used to directly associate real-world networks with the Watts and Strogatz model (Humphries and Gurney 2008). Incidentally, the small-world coefficient might not faithfully capture the small-world property as originally described by Watts and Strogatz (1998). Therefore, an alternative coefficient has been proposed that compares the clustering of the network to a lattice instead of a random network (Telesford et al. 2011). A large number of empirical network data conform to the small-world features of short paths combined with high clustering, including many neural networks—but do these Electronic supplementary material The online version of this article (doi:10.1007/s00429-015-1035-6) contains supplementary material, which is available to authorized users.

Stability and delay analysis of multi-layered GNR and multi-walled CNT interconnects

This paper analyzes and compares the propagation delay and relative stability of multi-layered GNR (MLGNR) and multi-walled CNT (MWCNT) for different interconnect lengths. The transfer function of a driver-interconnect-load system is obtained by representing the interconnect line with equivalent single conductor model of either a MLGNR or a MWCNT. Using the transfer function of distributed transmission line, an analytical expression of delay is obtained that exhibits significant accuracy. It is observed that a similar delay performance is obtained using fewer number of MWCNT shells than MLGNR layers. On an average, a MWCNT requires 54.5 % lesser area compared to MLGNR interconnects for the similar delay performance. Additionally, using Nyquist criterion, the relative stability of MLGNR and MWCNT is compared for local, semi-global and global interconnect lengths. It is observed that the relative stability of MLGNR is lesser in comparison to MWCNT at local interconnect lengths, whereas, encouragingly for semi-global and global interconnect lengths, both MLGNR and MWCNT demonstrate better stability characteristics.

Chinese immigrant youth identities and belonging in Prato, Italy: exploring the intersections between migration and youth studies

This article explores the experiences of young people of Chinese background in Prato (Italy). Despite significant social exclusion, young Chinese develop a sense of belonging to Prato by creating local, translocal and transnational affiliations and interconnections. These relationships contribute to making an often overtly hostile local reality, liveable and meaningful. A central aim of this article is to examine the intersection between migration studies and youth studies. The former tend to focus on the processes of identity formation featuring ethnic background, hence the label ‘second generation’. In contrast, the latter tend to foreground age- and generation-specific practices of belonging that may extend beyond ethnic identification, hence the focus on ‘youth’. We argue that bringing migration and youth studies together – by complicating notions of home and host, migrant and local identity and belonging – helps us to better understand how young people are managing multiplicity and mobility (and situatedness and stasis/fixity).

A Paradigm Shift in Local Interconnect Technology Design in the Era of Nanoscale Multigate and Gate-All-Around Devices

As the technology scales down to the sub-10 nm nodes, the interconnect performance becomes primarily dominated by the resistance rather than the capacitance due to the ever-increasing size effects of copper and a higher input capacitance of the devices. The implications of this paradigm shift are discussed in this letter, and it is shown that the local interconnect technology needs to be reoptimized to rebalance the interconnect resistance and capacitance. One approach is to increase the interconnect width beyond half pitch without changing the interconnect pitch. For the 5-nm technology node with an aspect ratio of 3, the energy-delay product of vertical field-effect transistor circuits at the optimal relative width improve up 55%, compared with the circuits using an aspect ratio of 2 and an interconnect width of half pitch.

Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.

Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs

Electromigration (EM) in power distribution networks (PDNs) is a major reliability issue in 3-D ICs. While the EM issues of local vias and through-silicon-vias (TSV) have been studied separately, the interplay of TSVs and conventional local vias in 3-D ICs has not been well investigated. This co-design is necessary when the die-to-die vertical power delivery is done using both TSVs and local interconnects. In this paper, we model EM for PDNs of 3-D ICs with a focus on multiscale via (MSV) structure, i.e., TSVs and local vias used together for vertical power delivery. We study the impact of structure, material, and preexisting void conditions on the EM-related lifetime of our MSV structures. We also investigate the transient IR-voltage change of full-chip level 3-D PDNs with MSVs with our model. The experimental results demonstrate that our EM modeling can effectively capture the EM reliability of the full-chip level 3-D PDNs with MSVs, which can be hard to achieve by the traditional EM analysis based on the individual local via or the TSV.

Dipolar emission in trench metal–insulator–metal waveguides for short-scale plasmonic communications: numerical optimization

Here we consider the numerical optimization of active surface plasmon polariton (SPP) trench waveguides suited for integration with luminescent polymers for use as highly localized SPP source devices in short-scale communication integrated circuits. The numerical analysis of the SPP modes within trench waveguide systems provides detailed information on the mode field components, effective indices, propagation lengths and mode areas. Such trench waveguide systems offer extremely high confinement with propagation on length scales appropriate to local interconnects, along with high efficiency coupling of dipolar emitters to waveguided plasmonic modes which can be close to 80%. The large Purcell factor exhibited in these structures will further lead to faster modulation capabilities along with an increased quantum yield beneficial for the proposed plasmon-emitting diode, a plasmonic analog of the light-emitting diode. The confinement of studied guided modes is on the order of 50 nm and the delay over the shorter 5 μm length scales will be on the order of 0.1 ps for the slowest propagating modes of the system, and significantly less for the faster modes.