Abstract

The performance of gigascale integration chips improves by cryogenic technologies such as subambient cooling. In these conditions, interconnects may perform at temperatures as low as 50 K. However, the local temperature of interconnects could easily be as high as 600 K at high-temperature chips. In this brief, we investigated the impact of temperature on delay of local, intermediate, and global interconnects of International Technology Roadmap for Semiconductors Node 2024. This is done for different values of interconnect width and length, nanotube diameter, and percentage of metallic carbon nanotubes (CNTs) in a grown bundle. Results are compared with those of copper counterpart. We showed that for local layers, a bundle of single-walled CNTs (BSWNTs) interconnects could outperform copper interconnects up to 17%, 35%, and 44%, respectively, at 50, 300, and 600 K, whereas for intermediate and global layers, there is a negligible difference between delay of copper and BSWNT interconnects at all temperatures.

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