Load Modulation Network Research Articles

A Compact Broadband Mixed-Signal Power Amplifier in Bulk CMOS With Hybrid Class-G and Dynamic Load Trajectory Manipulation

This paper presents a mixed-signal power amplifier (PA) with real-time hybrid Class-G and dynamic load trajectory manipulation (DLTM) operation that achieves PA efficiency enhancement into the deep power back-off (PBO) region. Moreover, we dynamically manipulate the PA load impedance trajectory that travels from the optimum output power ( $P_{\mathrm {out}}$ ) load impedance to the optimum efficiency load impedance during PBO, which creates PA PBO efficiency peaking. The introduced digitally intensive mixed-signal PA architecture enables precise and optimum real-time hybrid PA operation and ensures both PA output amplitude and phase accuracy. DLTM operation also extends the PA RF carrier bandwidth. A prototype PA is fully integrated in a standard 65-nm bulk CMOS process. Its load modulation network is realized by an on-chip compact transformer balun and two on-chip switch-controlled capacitors. The PA achieves +24.6-dBm (+24.4-dBm) peak $P_{\mathrm {out}}$ and 45.6% (45.8%) maximum drain efficiency (DE) at 2.4 GHz (2.8 GHz). DLTM operation extends the PA $P_{\mathrm {out}}~{\mathrm{ and}}~1$ -dB bandwidth from 41.7% to 53.8%. By combining the real-time hybrid Class-G and DLTM operation with mixed-signal linearization, the PA delivers +17.6/+17.3-dBm (+17.3/+17-dBm) 10M-Sym/s 64QAM/256QAM at 2.4 GHz (2.8 GHz) with 27.5/26.7% (26.2/24.1%) DE, −29.2/−30.4-dB (−31.3/−31.5 dB) rms error vector magnitude (EVM), and −25.3/−25.1-dBc (−26.4/−26.1-dBc) adjacent channel leakage ratio (ACLR). The total chip area is 1.9 mm2.

Watt-Level mm-Wave Power Amplification With Dynamic Load Modulation in a SiGe HBT Digital Power Amplifier

Performance limits and design techniques for Watt-level power amplification at millimeter-wave (mm-wave) frequencies using silicon germanium (SiGe) HBT Class-E power amplifiers (PAs) is presented in this paper. A Class-E power modulator architecture is proposed for demonstrating highspeed data transmission using ASK modulation at mm-wave frequencies. Several of these 1-b power modulators are power combined to realize a Watt-level digital PA with several levels of output amplitude at mm-wave frequencies. A dynamic load modulation concept is proposed to mitigate the effect of load pulling in the digital PA at power back-off. A tunable transmission line architecture with variable characteristic impedance is proposed to realize this dynamic load modulation network and enable efficiency enhancement at power back-off levels in the Watt-level digital PA. Watt-level power generation at mm-waves was demonstrated in a eight-way combined digital PA with dynamic load modulation, fabricated in a 0.13-μm SiGe BiCMOS process with ≈29 dBm (0.8 W) measured output power at 46 GHz, 18.4% peak power-added-efficiency, and 60% of the peak efficiency at 6-dB power back-off.

Improved Doherty Amplifier Design with Minimum Phase Delay in Output Matching Network for Wideband Application

This letter presents an improved Doherty power amplifier (DPA) for high-efficiency and wideband operations. To achieve the impedance transformations both in the low power region and at saturation, a design approach is proposed to determine the desired minimum phase delays of the carrier and peaking output matching networks, which can simplify the load modulation network of the DPA and extend the bandwidth. For verification, a 1.6-2.2 GHz asymmetric DPA was designed and measured. The designed DPA can deliver an efficiency of 51%-55% at 10 dB back-off power over the whole band. For a 20 MHz LTE signal, an average efficiency of higher than 50% can be achieved at 36 dBm average output power with the linearity of -48 dBc after linearization across the band.

A PAPR-Aware Dual-Mode Subgigahertz CMOS Power Amplifier for Short-Range Wireless Communication

A peak-to-average power ratio (PAPR)-aware dual-mode power amplifier (PA) for short-range wireless communication in the subgigahertz band is proposed in this brief. By carefully choosing the bias, the dual-mode PA achieves the measured output P1 dB (OP1 dB) of 13.6 dBm with a PAE of 25.5%. Furthermore, a dynamic load modulation network is utilized to optimize the PA's efficiency at back-off power. A power-control loop is proposed to detect the input signal PAPR in real time and flexibly reconfigure the PA's operation modes. With these proposed techniques, the PAE has been improved by ×2.61 at 7-dB back-off power. The measurement shows that the subgigahertz-band PA archives an adjacent channel leakage ratio (ACLR1) of −37.3 dBc and an average/peak error vector magnitude of −30.4 dB/−20.5 dB at 8.9-dBm output power for ∼5-dB-PAPR 16-quadrature-magnitude-modulation LTE signals with 5-MHz bandwidth with the power control loop enabled. The PAPR-aware dual-mode PA, powered by a 2-V supply, occupies a 2.52-mm2 die area in a 180-nm CMOS.

High-Efficiency GaN Doherty Power Amplifier for 100-MHz LTE-Advanced Application Based on Modified Load Modulation Network

This paper presents a high-efficiency GaN Doherty power amplifier (PA) with 100-MHz instantaneous bandwidth for 3.5-GHz long-term-evolution (LTE)-advanced application. A modified load modulation network, employing an enlarged peaking amplifier to carrier amplifier power ratio and moderately increased load impedance of the carrier amplifier, is proposed for enhancing efficiency and achieving improved load modulation. To increase the power ratio and alleviate the influence of slight impedance mismatch, a proposed load impedance strategy and corresponding stepped-impedance matching network are adopted for high-efficiency and wideband operation. By tuning the carrier offset line, the inconsistency of efficiency, gain, and output power in the operation band can be alleviated. Measurement results show that the Doherty PA has a drain efficiency of approximately 40% with gain fluctuation less than 0.5 dB at 9-dB back-off power, and maximum efficiency of about 60% at saturation in the signal band of 3.4-3.5 GHz. By using the digital pre-distortion (DPD) technique, the Doherty PA achieves adjacent channel leakage ratio of about -48 dBc at an average output power of 40.4 dBm with efficiency of 42.5%, when driven by 100-MHz LTE-advanced signal. To the best of the authors' knowledge, this is the first high-performance result of linearization using conventional DPD technique with 100-MHz bandwidth signals for the GaN Doherty PA at 3.5-GHz frequency band thus far.

Optimized Load Modulation Network for Doherty Power Amplifier Performance Enhancement

In this paper, a new load modulation network (LMN) is proposed for the Doherty power amplifier (DPA). By adjusting the transmission line characteristic impedances in the LMN, efficiency degradation due to the incomplete load modulation caused by the current unbalance between sub-amplifiers can be alleviated. Comprehensive theoretical analysis is conducted to investigate the impact of imperfect current profile on the overall efficiency and give rise to the judicious solution. To validate the new theory, two DPA prototypes based on GaAs pseudomorphic HEMTs are implemented for comparative purposes. Measurement results show that 8% and 13% greater power-added efficiency values are achieved at saturation and 6-dB output back-off point with the proposed method when compared with that of the conventional one. Additionally, the output 1-dB compression point is also improved by 2.9 dB. In particular, to the best of the authors' knowledge, this work provides a solution to address the inherent lower current driving ability for the peaking amplifier directly at the output part of a single-input DPA.