Ling Adder Research Articles

FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier

ABSTRACT The energetic growth in portable multimedia and mobile communication system has increased the requirement of high-speed signal processing system with compact area and power consumption. Finite impulse response(FIR) filters are broadly used in image, signal, speech and video signal processing, medical electronics, noise filtering, mobile communication and many other fields. The performance of the whole signal processing system with FIR filter depends on the basic building block of multiplier and adders. Hence, the hybrid FIR filter is proposed to improve the speed of the signal processing system using hybrid adder and hybrid multiplier. In this technique, the basic hybrid adder is designed with the help of 2-bit adders, BEC and 4:1 Multiplexer. Also, the hybrid multiplier is designed based on partial products of two consecutive multiplicand bits which are added at same time using Han-Carlson, Weinberger and Ling adder. The proposed FIR filter is functionally verified and synthesised using Xilinx ISE simulator and is implemented in Spartan 6 FPGA boards. The result shows that the delay of FIR filter using the proposed multiplier is improved by 26.51%, 15.59%, 15.83% and 2.79% as compared with CLA, conventional CSA, CSA-BK-BEC and the proposed adder with array multiplier, respectively.

High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation

The major role of electronic devices is providing low power dissipation and high speed with compact area. The speed of electronic devices depends on arithmetic operations. Multiplication is the important arithmetic operation in many VLSI signal processing applications. Hence, a high-speed multiplier is needed to design any signal processing module. Many multipliers are surveyed in the literature. They are Array, Wallace tree, booth, Vedic and Compressor-based multiplier. The speed of these multipliers depends on partial product accumulation. The hybrid parallel adder-based multiplier is proposed to improve the speed of multiplication compared to the existing technique. In this technique the partial products of, two consecutive bits (multiplicands), are added simultaneously with the help of a hybrid adder (Hancarlson, Weinberger and Ling adder). The proposed architecture is synthesized and simulated using Xilinx ISE 12.1 with various FPGA boards. Synthesized report shows that the speed of proposed multiplier (Spartan 6 FPGA implementation) is improved when compared to an Array multiplier (22.14%), Wallace tree multiplier (20.41%), Multiplier using compressor (13.89%), Vedic Multiplier using CLA (13.03%), Vedic Multiplier using RCA (3.54%), Modified Booth multiplier (4.42%) and Vedic Multiplier using HCA with BEC (3.28%).

A systematic design of novel energy efficient 64-bit parallel-prefix adder

ABSTRACT Advancement in CMOS technology demands to revamp the design of basic functional units in digital systems. The binary addition is the basic operation in digital units like microprocessors, digital signal processors and data processing units in ASICs. Scaling down the technology no longer supports power density and energy-efficient digital architectures. The energy-efficient adder design demands the exploration of recurrence structures, existing algorithms, circuit design techniques, system constraints, energy and delay trade-offs. This paper presents the systematic design approach towards the design of an energy-efficient 64-bit parallel-prefix adder. A novel two-bit sum block reduces the power dissipation and the proposed recurrence algorithm further optimises the overall energy consumption. The 64-bit adder is implemented in static CMOS design and simulated in 45, 32, 22 and 16 nm technology nodes to validate the energy efficiency. In 45 nm technology, the proposed 64-bit parallel-prefix adder consumes 64.61% and 15.3% less energy compared to Brent–Kung and Ling adder respectively whereas in 16 nm technology, the proposed adder consumes 57.54% lesser energy than Brent–Kung adder and 14.28% lesser energy compared to the Ling adder.

Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding

The need for hard (3X) multiple generation in radix-8 booth encoding increases the complexity of partial product generation and the latency of the multiplier. The source of delay is primarily the propagation of carry signals. A variety of carry propagate adder architectures have been studied to overcome this drawback. In this paper, we propose a hybrid adder architecture that precomputes the simultaneous generation of pseudo carry signals by exploiting the symmetry of 3X multiple and the final carry generation using Ling prefix network. As the Ling adder in the carry path reduces the complexity, the proposed adder results in significant improvement in the power delay product ($${\sim }$$25–55%) compared to state of the art 64 bit adders. This adder decreases the number of logic gates in the critical path, leading to a reduction in static power consumption. As a design metric, it is necessary to minimize the energy dissipation of logic modules, the results indicate that the proposed hybrid adder would fulfil the requirements of processors in deep sub-micron VLSI technology.

Design and Implementation of 32-Bit High Valency Jackson Adders

Parallel prefix addition offers a highly efficient solution to most of the applications which requires fast addition of two binary numbers. An efficient adder design demands proper selection of recurrence equations and its realization. There are different recursion equations like Weinberger recursion, Ling recursion, Jackson recursion, to name a few, available to suit a variety of design requirements. In this work, we have proposed adders based on Jackson recursion. In these adders, the complexity found in generate term is reduced at all the levels of the carry graph to optimize the adder performance parameters. The proposed adder structures are implemented for a word size of 32-bit based on the Jackson recursion equations for valency-4 and valency-5. The synthesis results reveal that the high-valency Jackson adder structures are superior in terms of power and area over the Ling adders for comparable delay values. Experimental results obtained reveals that an average of [Formula: see text] and [Formula: see text] savings in area and power, respectively, are achieved by the proposed adders, as compared to Ling adders for the same word size. Furthermore, the proposed adders demonstrate enhanced area-delay and the power-delay values compared to the adders based on the Weinberger’s recursion.

Novel High-Performance High-Valency LingAdders

Parallel prefix adders are used for economical VLSI implementation of binary variety additions. The proposed Ling design offers a quicker carry computation stage compared to the standard parallel prefix adders by projecting a replacement methodology to solve Ling adders, which helps to cut the complexity and also the delay of the adder. This paper discusses the look and implementation details for such lower complex, quick parallel prefix adders supported Ling theory of resolving. Specifically, valency or node indicates number of inputs given to a particular node in a carry tree. The proposed ling adder shows that the high-valency Ling adders have superior space area and delay characteristics over antecedent reportable adders for identical input size. Moreover, our 20-bit high valency adder features a higher space and delay measuring than the antecedent used 16-bit adders.

Area Efficient Hybrid Parallel Prefix Adders

Addition is a timing critical operation in almost all modern processing units. The performance parameters such as the implementation area, the adder latency and the power dissipation decide the choice of adders for different applications. Hence, there is an extensive research attention towards designing higher speed and less complex adder architectures with lower power dissipation. Among the several adder topologies available, parallel-prefix adders are the most frequently employed as they offer many design choices for achieving area/power/delay efficiency and they also provide optimization of the trade-offs. This paper discusses the design and implementation of area-power optimized hybrid parallel-prefix Ling adder. The hybrid adder topology employed in this work uses Ladner-Fischer approach for even-indexed and Kogge-Stone structure for odd-indexed bits. The independent computation of carries for odd and even bits, directly leads to the reduction of fan-out of the prefix tree and thereby a reduced delay. The area efficiency is achieved by the computation of the real carries using modified Ling's equations. The proposed adders are implemented with word size of 16 bit and 32 bit based on modified Ling equations using 0.18μm CMOS technology. The synthesis results reveal that the proposed adders could achieve up to 24% and 35% saving of area-power product and power-delay product respectively, over the adders based on conventional Ling equations.

IMPLEMENTATION OF 32-BIT HIGH-VALENCY LING ADDER IN MODIFIED FIR FILTER USING APC-OMS APPROACH

Ling Adder is an advanced architecture of Parallel prefix adders. Parallel Prefix adders are used for efficient VLSI implementation of binary number additions. Ling architecture offers a faster carry computation stage compared to the conventional parallel prefix adders. Ling adders help to reduce the complexity as well as the delay of the adder further. In many computers and other kinds of processors, adders are used not only in the Arithmetic Logic Unit (ALUs), but also in other parts of the processor. Thus the delay in adders has to be decreased as maximum as possible to make the system faster. In particular, valency or the number of inputs to a single node is explored as a design parameter. High-valency Ling adders have superior area x delay characteristics over previously reported Ling-based or non-Ling based adders for the same input size. In DSP, even the multipliers require a large number of logic gates that consumes more area, power and delay. Hence, the lookup table can be used for performing computation which requires less area. Therefore, APC and OMS are the two techniques implemented in Lookup table so as to reduce the size to one-fourth of its conventional multiplier. This proposed combination of both Lookup table Multiplier and Ling adder has a better area and delay measurement.

Design of High-Speed Adders for Efficient Digital Design Blocks

The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

Verification and synthesis of addition programs under the rules of correctness of statements

Deductive verification and synthesis of binary addition programs are carried out on the base of the rules of proving the correctness for statements of the predicate programming language P. The paper presents key fragments of verification and synthesis of the programs for the Ripple carry, Carry look-ahead and Ling adders. The correctness conditions of the programs were translated into the specification language of the PVS verification system. The proof is found to be a tedious procedure as compared with the ordinary programming. However, for program synthesis, the development of theories and proofs on PVS are easier and faster than for program verification.

An efficient architecture for accumulator-based test generation of SIC pairs

Research conducted over the years has shown that the application of single input change (SIC) pairs of test patterns for sequential, i.e. stuck-open and delay fault testing is extremely efficient. In this paper, a novel architecture for the generation of SIC pairs is presented. The implementation of the proposed architecture is based on Ling adders that are commonly utilized in current data paths due to their high-operating speed. Since the timing characteristics of the adder are not modified, the presented architecture provides a practical solution for the built-in testing of circuits that contain such adders.

High-speed parallel-prefix VLSI Ling adders

Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well-suited for VLSI implementations. A novel framework is introduced, which allows the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of implementation compared to the parallel-prefix structures proposed for the traditional definition of carry lookahead equations and reduces the fanout requirements of the design. Experimental results reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the fastest parallel-prefix architectures presented for the traditional definition of carry equations.

Variants of an improved m-valued carry look-ahead adder

An improved m-valued carry look-ahead adder has been described by Manzoul et al. It is based on Ling's type of binary adder. Ling's adder is faster and less expensive than the conventional carry look-ahead binary adder. In this paper, the concept of Ling's approach is explained with a map-method first. Then a few improved m-valued carry look-ahead adders are proposed.

Variants of an improved carry look-ahead adder

An improved variation on the carry look-ahead adder has been proposed by H. Ling (IBM J. Res. Develop., vol.25, p.156, May 1981). Ling's approach is based on the propagation of a composite term in place of the conventional look-ahead carry. This approach gives an adder that is faster and less expensive. In the present study, Ling's adder is introduced and described in a general manner in order to expose the essence of his approach. From this reformulation, it is shown that there are many such variations on the carry look-ahead adder, a few of which share the desirable properties of Ling's adder. >