Oxide Liner Research Articles

Surface Roughness, Hardness and FTIR of the Modified Soft Liner with Different Metal Oxide Nanoparticles

Aims: To study the effect of metal oxide nanoparticles (MgO, ZrO2, ZnO) on acrylic based soft liner surface properties and FTIR. Materials and Methods: Acrylic-based soft-liner specimens were prepared by adding three different concentrations (0.5, 1, and 2) %wt of metal oxide nanoparticles (MgO, ZrO2, ZnO). A disk-shaped specimens with 30mm diameter and 3mm thickness were prepared for shore (A) hardness test to evaluate the surface hardness of modified soft liner. The surface roughness of soft-liner samples (10X10X2mm) was tested by a profilometer. FTIR analysis was conducted to evaluate chemical reaction that may occur between acrylic-based soft liner and nanoparticles. Results: there were no chemical reaction carried out between soft liner and metal oxide nanoparticles at different concentration- surface hardness (shore A) was increased as nanoparticles concentration increased in modified resin. Nanoparticles with 1 and 2% concentration incorporated in soft liner had lower surface roughness value. Conclusions: Metal oxide nanoparticles have improved the surface texture of acrylic-based soft liner, while the hardness of modified soft liner was increased with nanoparticles concentration increases.

A Scalable, Hierarchical Rib Design for Larger-Area, Higher-Porosity Nanoporous Membranes for the Implantable Bio-Artificial Kidney

Silicon nanoporous membranes provide the fundamental underlying technology for the development of an implantable bio-artificial kidney. These membranes, which are comprised of micromachined slit-pores that are nominally 10 nm wide, allow for high-efficiency blood filtration as well as immunoprotection for encapsulated cells. Our approach takes advantage of well-established semiconductor fabrication technology to give us precise dimensional control over pore widths, thereby enabling a highly selective filtration function and a clear path towards further miniaturization. This work builds on our prior results on “ribbed nanoporous membranes” by adding a second-level hierarchy of significantly taller “mega-ribs” to further strengthen the membranes. Relying on a two-step Deep Reactive Ion Etch (DRIE) process, we etch $4~\mu \text{m}$ -deep as well as $40~\mu \text{m}$ -deep trenches into a silicon substrate, grow a thermal oxide liner, and deposit a layer of polysilicon into this “mold” to form membranes which, when released after a backside DRIE etch, feature a network of reinforcing ribs on the underside. We have fabricated and tested freestanding membrane spans that are up to 14 times wider than before, with approximately double the measured permeability per unit area. The new architecture can also improve cross-membrane mass-transfer rates and reduce chip-fabrication costs. [2020-0170]

Crosstalk noise minimization in novel through silicon via structures

In recent trends, through silicon via (TSV) is essential Technologies for 3-D IC integration because of its short interconnects length and high interconnect density. Beyond the existing structure of TSV, this paper provides a novel structure to investigate the crosstalk effect and same is simulated by using a SPICE simulator and 3-D field solver. The structure of the TSV comprises of copper surrounding by insulating liner, and silicon substrate. In existing structures, silicon dioxide (Sio2) is used as insulating liner because of its material compatibility with silicon substrate. Several researches provide the problem of using Sio2 is due to its high dielectric constant; as a consequence delay will increase. Therefore, Sio2 is not appropriate for high performance applications. In this work, a novel TSV structure is reported to improve the TSV performance which uses poly-propylene polymer liner instead of oxide liner. Signal TSV is enclosed by using a poly-propylene liner and amid the analysis with doping region is created around the ground TSV. For comparison purposes, conventional and proposed TSV structures are simulated. The proposed TSV’s structure simulation results in 30% decrease in crosstalk over existing TSV structures.

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

Generation and elimination of silicon pitting for 300 mm CMOS process technologies

The complementary metal oxide semiconductor (CMOS) process technology in a 300 mm wafer fab experienced wafer center yield loss. In-line wafer defect inspection revealed gross silicon pitting at the wafer center as the root cause of the yield loss. Affected dies showed pitting at the interfacial corner between the silicon substrate and the isolation oxide. The mechanism of silicon pitting involves creation of silicon microdefects during several high-temperature furnace anneal process steps (liner oxide and posthigh energy phosphorus implant anneals) because of local die and global wafer level thermally induced mechanical stress at the silicon substrate to isolation oxide interfacial corner. In addition, implant-induced silicon microdefects from a high energy (>2 MeV) phosphorus implant, extending to the silicon surface provide a further significant contribution to the silicon microdefect population. The overall microdefect population is further aggravated by Ostwald ripening during a subsequent thick silicon-oxide furnace growth process, resulting in sufficient corner silicon microstructure damage to enhance wet-etching during a subsequent wet-clean leading to gross silicon pitting. Silicon pitting is eliminated by lowering either the liner oxide or postimplant anneal temperatures or skipping the high energy phosphorus implant. Incorporating a reduced liner oxide anneal temperature into the CMOS process flow eliminated the wafer-level yield loss at the wafer center associated with gross silicon pitting defects.

Novel integration of ultrathin Al2O3 with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

Through-silicon-via (TSV) used in three-dimensional (3D) stacked dies must present small electrical parasitic, such as capacitance, to allow for low latency signal transmission. Stable TSV capacitance is desired to overcome the spatial circuit performance variation caused by non-uniform hot-spot heating. In this work, a novel combination of low-k with ultrathin Al2O3 bilayer liner is successfully integrated in the TSV. The TSV capacitance is reduced by ∼26% as compared to plasma-enhanced tetrahydrothosilicate (PETEOS) oxide liner. Stable TSV capacitance within the operating voltage of interest (∼0–5 V) is achieved by operating the TSV in a stable accumulation capacitance region. The positive shift in the flat-band voltage (ΔVFB = +19 V) is achieved by utilizing Al2O3-induced negative fixed charge (|Qf| = 1.3 × 1012 cm−2) at the Si/low-k interface. Leakage current density of the bilayer liner is improved to a level comparable with the PETEOS oxide liner post annealing [forming gas (N2/H2) at 350 °C for 2 h or 400 °C for 0.5 h]. Low-k material with a smaller elastic modulus improves the thermo-mechanical stress exerted on the surrounding Si substrate compared with PETEOS oxide.

Dielectric liner reliability in via-middle through silicon vias with 3 Micron diameter

In high aspect ratio through silicon vias (TSV's), the trench step coverage (conformality) of liner, barrier and seed is critical for both the process integration and reliability. If the conformality of a deposition process is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3μm and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctrl) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100°C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS oxide liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD oxide liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications.

Impact of electrical and thermal stresses on TSV radiofrequency performance

This paper presents a study of the propagation parameters (impedance and propagation constant) for interconnection structures implementing interconnection lines (wafer front and backside) combined with Through Silicon Via (TSV). Lifetime acceleration experiments are conducted on these structures and indicate a significant variation of the propagation parameters across lifespan. The underlying physical mechanism is demonstrated and an activation model for the prediction of the line parameter variation is proposed. TSV-last processes have been considered by industry for the implementation of 3D interconnects into various kind of silicon substrates already functionalized on the front side. This is possible thanks to a TSV process with a low temperature budget (<200°C), guaranteeing the compatibility with most of the pre-existing MOS and passive technologies. IPDiA is offering this type of TSV technology in combination with the PICS passive platform (Passive Integrated Connecting Substrate). Several test vehicles have been implemented and excellent performances have been observed in the small signal/RF domains; electrical models have been extracted from test silicon and are showing a good agreement with simulation results and earlier literature. Application domains with permanent bias have also been considered and non-linear effects related to the semiconductor nature of the substrate have been reported (i.e. drift-diffusion). However, the effect of electrical and thermal stress that might arise from severe applications or long lifespan, and their impacts on TSV electrical stability, have not yet been reported in the literature. This works concentrates on the study of the instability modes that are related to the TSV dielectric aging under permanent bias accelerated by temperature. To avoid effects from other mechanisms (like, for example, copper diffusion in the oxide) under the selected acceleration conditions (Efield<10MV/cm, temperature <100°C), specific test structures (planar CPW) are designed. It consists of an AlSi (0.5%) metallization, which is isolated from the P type HR (High Resistivity) substrate by TSV isolation dielectric. Four different flavors of dielectric are proposed: PECVD oxide deposited at 150°C/200°C combined/not with a thermal oxide liner. When implemented, the liner is intended to enhance the dielectric/silicon interface, thus allowing to differentiate the effects of fixed charges, mobile charges, and interface states density. A strong correlation is found between charge density within the dielectric and the CPW loss and characteristic impedance. While line loss increases with charge density, the opposite behavior is observed for the characteristic impedance. Furthermore, under CVS (constant voltage stress) at 7.5 MV/cm under 100°C, a displacement of mobile charges into the dielectric is observed, that correlates to the variation of the CPW performances. FTIR analysis indicates that the mobile charges are related to the presence of silanol/hydroxide ions resulting from moisture absorption in the oxide. Similar effects are observed on real 3D TSV structures. An activation model is derived from previous results, which allows predicting the evolution of the CPW characteristics as a function of thermos-electrical stress.

The improvement of MOSFET performance by the optimization of STI HDP-CVD integration process

The integration process of shallow trench isolation (STI) deposition was systematically investigated by using high-density plasma chemical vapor deposition (HDP-CVD). Two sputtering agents, Ar and H2, were utilized with various plasma RF power conditions. The STI HDP-CVD process consisted of two steps, including liner oxide and main gap-fill depositions. For the liner oxide deposition, the usage of Ar plasma was more favorable than H2 plasma because the drift of hydrogen-ions was detrimental for the electrical property of gate oxide. In the gap-fill process, H2 plasma with high bias RF power efficiently reduced plasma charging damage (PCD) on gate oxide due to its low sputtering rate and densely filled STI. The gap-fill capability and PCD were improved by the optimized condition of STI HDP-CVD process.

Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application

Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson's equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 $\mu \hbox{m}$ . After presenting the fundamental $C$ – $V$ characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window ( $\vert{V}_{\rm ow}\vert=\hbox{20} \hbox{V} $ ) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge $Q_{\rm ot} $ engineering in TSV oxide liner, neither considerations of the ${V}_{\rm FB} $ shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously.

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias

The reliability results for barrier/liner systems in different high aspect ratio (5×50μm) through silicon vias (TSV) are presented. Quite a few factors can influence the TSV barrier/liner reliability performance, including the TSV trench etch process, the oxide liner material/thickness, etc. The challenges for more advanced TSV technology nodes (e.g. 3×40μm) are also discussed and possible solutions are proposed.

Alternative to H3PO4 for Si3N4 removal by using chemical downstream etching

Si3N4 is widely used in the semiconductor industry as a sacrificial etch stop layer, implantation spacers, hard mask for selective epitaxy. Si3N4 is resistant to many RIE process, to fluoridric acid, and can be easily removed thanks to hot phosphoric acid with excellent selectivity to other materials (Si and SiO2). However hot phosphoric process presents majors drawbacks: Done in wet benches, the levels of metallic and particular contamination, process uniformity, do not match all the requirements of 14nm node and beyond. Surface preparation standards indeed converge towards single wafer cleans for these reasons. But typical etch rate with hot phosphoric are too low (>1Å/min) to be compatible with a single wafer approach.Plasma removal is a possible alternative, either by RIE or CDE (Chemical Downstream Etching). If the selectivity to the SiO2is usually very low for RIE (~15), selectivity for CDE reactors up to 60 have been reported in the last years, increasing the interest for this technique.In the present work we evaluated the etching selectivity of a new CDE process. We achieved successfully its integration in replacement of hot phosphoric acid for a process step denoted as nitride pull back (NPB): In VLSI circuits, transistors are electrically insulated by trenches filled with SiO2. As the filling is done by conformal deposition methods, it is greatly facilitated by an etch back of the top Si3N4 (fig.1). One problem in this case is that CDE used here could etch the silicon in the trench very quickly: this disadvantage has been overcome by oxidizing the flanks of the trench with a RTP process. In this configuration, a SiO2 liner is formed at the surface of the trench. However RTP process is known to create also an oxidized layer at the surface of the Si3N4 that can delay the etching.In this context we evaluated the selectivity of the process on full sheet layers. For that purpose we generated SiN layers made by LPCVD furnace at 770°C, and thermal SIO2 made by RTP. Top of the Si3N4layers were also oxidized to evaluate the etching delay induced by this surface oxidation.Fig2. reports the Si3N4 and SiO2 etch rates vs. etching time. Si3N4 removal rate is very stable around 150 Å/min. In the same time SiO2 etch rate increases moderately form 0.6 to 1.6 Å/min. As a result, the average selectivity is always higher than 100:1 and reaches 250:1 at the early stage of the process. If oxidized, an etch delay is induced and Si3N4 etch rates and selectivity to SIO2 drops rapidly with the oxidation budget (fig.3): Thus a moderate oxidation has been done on the patterned wafer to preserve both Si3N4 etch rate and the liner integrity. Thickness measurements returned a Si3N4 removal of 120Å with a good within wafer uniformity (3.5%), and a negligible SIO2 removal (<0.1Å). TEM cross sections (Fig.4) confirmed that the oxide liner and underlying silicon are preserved during the Si3N4 etching.Differences of etch rates between dense and isolated areas have been evaluated as far as the defectivity aspects and will be discussed in the full paper.

Hydrogen outgassing induced liner/barrier reliability degradation in through silicon via's

Degraded liner/barrier integrity is observed in 3D Cu through silicon via systems using a sub-atmospheric chemical vapor deposition O3/tetraethyl orthosilicate (TEOS) oxide liner and a physical vapor deposition Ta barrier. By analyzing the data of thermal desorption spectroscopy and Fourier transform infrared spectroscopy, the source of the degradation is found to be outgassed hydrogen from the liner. To overcome this hydrogen induced degradation, three alternative liner/barrier schemes are proposed and validated: 1) a capped O3/TEOS liner, 2) a metal barrier that is resistant to hydrogen, and 3) a denser oxide liner.

Barrier Properties of CVD Mn Oxide Layer to Cu Diffusion for 3-D TSV

The effect of CVD Mn oxide layer as a barrier layer to Cu diffusion for 3-D TSV was characterized. The impact of oxide substrate on the barrier property of a planar Mn oxide was evaluated by XPS method. Planar Mn oxide layer of 20-nm thickness formed over thermal oxide showed an excellent barrier property to Cu diffusion after annealing at 500°C, whereas the Mn oxide over P-TEOS oxide was good enough up to 400°C annealing. On the other hand, the barrier property of Mn oxide upon O3-TEOS oxide was not as good as thermal and P-TEOS oxides. The effect of a vertical Mn oxide layer as a barrier layer to Cu diffusion from Cu TSV was evaluated by C-t analysis. Vertical Mn oxide layer with 20-nm thickness formed on P-TEOS oxide liner in TSV showed better barrier property, when compared with the sputtered Ta barrier layer, up to 400°C annealing condition. However, the barrier property of CVD Mn oxide layer was degraded after annealing at 500°C.

단일구조 지르코니아(zirconia) 전부도재관의 표면처리에 따른 전장도재와의 전단결합강도

Purpose: The aim of this research was to investigate difference in shear bond strengths of full-contour zirconia layered with porcelain. Methods: Disk-shaped (diameter: 12.0 mm; height: 3.0 mm) zirconia were randomly divided into six groups according to the surface conditioning method to be applied (N=90, n=15 per group): group 1-contol group(ZC); group 2-airborne particle abrasion with <TEX>$50-{\mu}m\;Al_2O_3(5A)$</TEX>; group <TEX>$3-50-{\mu}m\;Al_2O_3$</TEX> + liner(5AL), group <TEX>$4-110-{\mu}m\;Al_2O_3(1A)$</TEX>; group <TEX>$5-110-{\mu}m\;Al_2O_3$</TEX> + liner(1AL); group 6-liner(LC). On each block, zirconia porcelain was build up according to manufacturer's instructions. All samples were fixed with measuring jigs and shear bond strength were measured with Universal testing machine. Collected data were analyzed using SPSS(Statistical Package for Social Sciences) Win 12.0 statistics program. Results: LC showed the highest value(<TEX>$29.92{\pm}2.55$</TEX> MPa) and ZC showed the lowest value(<TEX>$13.22{\pm}1.37$</TEX> MPa). Zirconia liner and Alumina oxide groups was significantly higher shear bond strength than control(p<0.05). 5A (without liner <TEX>$22.18{\pm}2.37$</TEX>, with liner <TEX>$22.84{\pm}1.74$</TEX> MPa) was higher shear bond strength than <TEX>$110{\mu}m$</TEX> (without liner <TEX>$20.18{\pm}2.38$</TEX>, with <TEX>$20.71{\pm}2.67$</TEX>). Conclusion: Surface treatments may have advantage in bond strength improvement for full-contour zirconia layered with porcelain.

Failure mechanism of copper through-silicon vias under biased thermal stress

We report the failure of copper through-silicon via (TSV) under biased thermal stress. The time-dependent dielectric breakdown (TDDB) of the oxide liner in the TSV was measured to detect the migration of copper from TSV to silicon. The breakdown of the oxide liner occurred by thermal cracking followed by fast drift of copper ions through the crack. For the TSV structure, there were an initial decrease in the leakage current and then the breakdown of oxide, which is different from the 3-stage TDDB behavior observed in the planar metal-oxide-semiconductor (MOS) structure. Micro-cracks in the oxide liner at the top corner of TSV were observed after TDDB measurement, and the thermal cracking of the oxide was caused by the expansion of copper TSV at test condition. Finite element analysis showed the tensile stress of 670MPa concentrated at the top corner of the TSV. The mechanism of TDDB in both TSV and planar MOS structures were also described comparatively.

Evaluating Oxide Liner and Copper Barrier Integrity of Through-Silicon-Via by Electrical Characterization and Microanalysis

ABSTRACT3D integration enabled by through-silicon-via (TSV) allows continued performance enhancement and power reduction for semiconductor devices, even without further scaling. For TSV wafers with all Applied Materials unit processes, we evaluate the integrity of oxide liner and copper barrier by capacitance-voltage (C-V) and current-voltage (I-V) measurements, from which oxide capacitance, minimum TSV capacitance, and leakage current are extracted. The capacitance values match well with model predictions. The leakage data also demonstrate good wafer-scale uniformity. The liner and barrier quality are further verified with microanalysis techniques.

Electrical characterization of TSVs with varying process knobs and temporary bond/adhesive system robustness studies for 2.5D/3D manufacturing

TSVs are used to carry power/ground and signals straight to the heart of the logic/memory devices where all the intricate and busy architectures lie. I consider it like the downtown area inside a city where the real estate is more expensive and requires intricate design and execution. As a result in case of the TSVs, there is no room for electrical degradation and stress interaction with transistor devices (keep out zone). The Cu protrusion, it's interaction with the intricate local interconnects (M1 and below structures), the current leakage, capacitance, reliability, become highly critical to fully achieve the power per watt advantage of the TSVs. As a result, a thorough electrical characterization of TSVs with varying film properties and the process window becomes very critical for integration with the 20nm node (and below) devices. In this paper we will discuss implementation of modified oxide liner, barrier/seed, ECD fill and CMP of films to achieve robust TSVs for electrical parameter extraction. We will closely examine the impact of these film properties on the electrical performance and its repeatability to achieve wide process windows. Such studies are expected to improve manufacturing yields of TSV product wafers at fabs/foundries. Alternately, we will present detailed metrology studies of two temporary bond method/adhesive systems as it progresses through the thin wafer downstream processes (via-reveal processes). This exercise is targeted to address productivity and yield challenges with thin wafer processing (backside via-reveal process). We will attempt to demonstrate a robust temporary bond/adhesive system that exhibits no thin wafer damage/wrinkling and no edge profile degradation issues over repeated runs (production like). This study will help to characterize the adhesive and low temperature passivation film interfaces in details to support the thin wafer processing robustness for TSV manufacturing.

Application of Low-k Liner for Stress and Capacitance Control in Cu-TSV

Through silicon via (TSV) is commonly fabricated by high aspect ratio deep silicon etching, lining with dielectric layer for electrical isolation and super-conformal filing with copper. It has been reported that Cu-TSV can exert thermo-mechanical stress on Si due to coefficient of thermal expansion (CTE) mismatch. This stress can result in undesired device mobility variation and structural reliability. In addition, TSV parasitic capacitance has the most predominant impact on the circuit operation. It is therefore imperative to reduce the TSV stress and capacitance. One solution is to use low-k dielectric as the liner since it has much lower elastic modulus and effective permittivity. In this work, low-k dielectric is successfully integrated in TSV as a liner. The implications on TSV stress, capacitance and leakage current are discussed. Due to its smaller elastic modulus (~7.2 GPa), the selected low-k carbon-doped oxide acts as a compliant layer to cushion the Cu-TSV stress on the Si compared with conventional oxide (75 GPa) by plasma enhanced chemical vapor deposition. This effectively reduces the near-surface compressive stress in Si by &amp;gt;25% compared with the conventional liner which is more rigid. Since the low-k liner has an effective dielectric constant of ~2.8, it is found that the integration of the low-k liner reduces the TSV capacitance by ~26% as compared with the conventional oxide liner. In summary, this work has provided evidence of the technical merits of a low-k material to mitigate the undesired Cu-TSV induced stress in the surrounding Si and the related parasitic capacitance.

Comparison of beryllium oxide and pyrolytic graphite crucibles for boron doped silicon epitaxy

This article reports on the comparison of beryllium oxide and pyrolytic graphite as crucible liners in a high-temperature effusion cell used for boron doping in silicon grown by molecular beam epitaxy. Secondary ion mass spectroscopy analysis indicates decomposition of the beryllium oxide liner, leading to significant incorporation of beryllium and oxygen in the grown films. The resulting films are of poor crystal quality with rough surfaces and broad x-ray diffraction peaks. Alternatively, the use of pyrolytic graphite crucible liners results in higher quality films.