ADC Linearity Research Articles

A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test

—The built-in self-test (BIST) circuit is designed to be highly integrated with ADC under test and tests the static linearity based on the stimulus error identification and removal (SEIR) method. A novel level shift generator is proposed for high-precision ADC testing to break the resolution limitation caused by thermal noise and non-linearity. The double sampling operation realized by the chopper circuits cancels the sampling kT/C noise, and the circuit further reduces the amplifier's thermal noise by reducing the noise bandwidth. Besides, this paper presents a new method to achieve a highly linearity-constant voltage shift by applying the negative-C technique. Implemented in 180 nm CMOS process, the simulation results show that the noise power of the voltage shift is reduced by 10 dB, and the constancy of voltage shift is only 3.7 ppm over the entire ADC input range. Benefitting from the noise and linearity performance enhancement, this BIST circuit can test 18-bit ADC to 18-bit accuracy level with one-tenth sampling points.

A ENOB 10.3 bit, 103 μW ON-CHIP CALIBRATION SAR ADC

Across the board, the performance of ADCs has been under increasing scrutiny because of the rapid growth of portable electronic devices and biomedical sensors. As part of the sensor’s long-term work, its power consumption should also be as low as possible. Sensors benefit from SAR ADCs’ small size and low power consumption, making them an ideal fit for ADCs. To overcome the limitations of accuracy and linearity of ADCs caused by manufacturing process deviations, a 12-bit, 1 MS/s low-power SAR ADC based on 180 nm CMOS technology is presented. The front-end analog calibration system ensures the ADC is at its best. The design also includes low fan-in SAR logic to reduce the capacitive load on the comparator and increase the comparison speed. The layout area is 0.3 mm2, approximately 30% less than conventional products of the same process.

LMS-based digital background mismatch calibration technique for SAR ADC

This paper proposes a digital background calibration technique based on the Least Mean Square (LMS) algorithm to suppress non-linearity in the SAR ADC. The calibration scheme does not significantly increase the complexity or scale of analog circuits. To evaluate the effectiveness of the proposed calibration scheme, we conducted 200-run Monte-Carlo simulations of a multi-segmented 20-bit SAR ADC using MATLAB. The simulation results demonstrate that the average values of SFDR and THD significantly improve from 60.9 dB and −59.2 dB–130 dB and −129.5 dB, respectively, under 1% capacitor mismatch. It is indicated that the proposed calibration scheme can significantly enhance the linearity of the SAR ADC.

A capacitor mismatch calibration scheme for SAR ADC based on genetic algorithm

AbstractCapacitor mismatch problem due to process variation causes weight error, which deteriorates the linearity of SAR ADC. In this paper, a novel calibration scheme based on genetic algorithm(GA) combined with a radix‐less‐than‐2 SAR ADC is proposed to extract the weight error caused by capacitor mismatch. This is a foreground calibration scheme and no extra injections are added. The proposed GA‐based calibration scheme is simulated based on 40 nm CMOS technology. After calibration, ENOB increases from 10.19 bits to 11.46 bits, INL changes from +2.22/−2.12 LSB to +0.81/−0.80 LSB, and DNL changes from +1.79/−1.00 LSB to +0.99/−1.00LSB. As can be seen from the simulation results, the proposed calibration scheme can effectively improve the linearity deterioration caused by capacitor mismatch.

A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62-<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/&#x2212;1 and 4.78/&#x2212;3.31 LSB, respectively.

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems.

This paper presents a 14-b 20-MS/s energy-efficient SAR ADC in 65-nm CMOS technology for portable medical ultrasound systems. To break the limitation of the ADC linearity on the DAC size in a SAR ADC, a background mismatch calibration technique is employed. As a result, the thermal noise will be the major constraint for the DAC size. In addition, a compact noise-reduction technique is proposed to alleviate the adverse impact of the input-referred comparator noise on the effective resolution. Moreover, a 2.5-V on-chip LDO, which serves as the reference generator for the ADC core, is also integrated to guarantee the reference accuracy and to suppress the supply noise. To reduce the capacitive load of the comparator and boost the comparison speed, a low fan-in SAR logic is also designed. With the proposed mismatch calibration technique and the noise-reduction technique activated, measured results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 78.8 dB and 95.4 dB, respectively. At 20 MS/s, the ADC consumes 6.8mW from its 1.2 V/3.3V supplies in total, leading to an SNDR-based Schreier FOM of 170.5 dB at Nyquist. The active area of the ADC is 450 × 540μm2.

Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies

Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies

A Low Power SAR ADC with Digital Error Correction Technique for Wearable and Implantable ECG Devices

Aims: This study aims to propose an 8-bit differential input low-power Successi,e Approximation Register (SAR) ADC with digital error correction technique for sensing bio-potential signals in wearable and implantable devices. Background: As dynamic comparators have the advantages of full swing output, low power consumption, high speed, and high impedance at the input, they are preferably used in energy-efficient SAR ADC’s. However, since the dynamic comparator is the most frequently used block in SAR ADC, research is ongoing to reduce its μW power further. Also, as the offset voltage of the comparator affects the linearity of ADC, it must be minimized. Linearity can further be improved by calibrating the output of ADC, and extensive surveys on the calibration methods prove that the addition- only digital error correction method is efficient in terms of power. Objective: The objective of this study is to design a low-power and low-offset dynamic comparator intended for SAR ADC to achieve highly linear digital output. In addition to this, the objective is to implement a power-efficient digital error correction technique for the output of SAR ADC to overcome the non-idealities due to process variations. Method: As power consumption is proportional to the number of transistors, the proposed comparator is a design obtaining the same output as the existing dynamic comparators with reduced transistor count. The proposed comparator, along with low power full swing three-input XOR logic gate, is implemented in SAR ADC with digital error correction technique in cadence 45 nm technology files, and its performance parameters are simulated. Results: The layout of the proposed dynamic comparator occupies an area of 3 μm2. The simulation results of this comparator with a load of 1 pF show that it has a total offset of 11.2 mV, a delay of 0.9 ns, and power consumption of 24 nW. It also achieves a gain of 49.5, i.e., 33.86 dB. The 8-bit ADC, along with the digital error correction technique operating at 143-kS/s and under 0.6 V supply voltage simulated in 45nm technology, consumes only 0.12 μW of power. The DNL and INL errors obtained are +0.22/-0.2 LSB and -0.28 LSB, respectively. SNR limited by noise is 48.25 dB, SFDR is 48.64 dB, and ENOB achieved is 7.72. Conclusion: To satisfy the requirement of the wearable and implantable devices, a low-power SAR ADC with good linearity is designed using a low-power and low-offset dynamic comparator. A digital error correction technique using a low-power XOR logic gate is implemented at the SAR ADC output to minimize the non-idealities due to the process variations.

Mixed-mode Method Used for Pt100 Static Transfer Function Linearization

Abstract Pt100 is a resistance temperature detector characterized by a relatively linear resistance/temperature relationship in a narrow temperature range. However, the Pt100 sensor shows a certain degree of static transfer function nonlinearity of 4.42 % in the range between −200 °C and 850 °C, which is unacceptable for some applications. As a solution to this problem, a mixed-mode linearization method based on a special dual-stage piecewise linear ADC design is proposed in this paper. The first stage of the proposed dual-stage piecewise linear ADC is performed with a low-complex and low-power flash ADC of a novel sequential design. The novelty of the proposed sequential design is reflected in the fact that the number of employed comparators is equal to the flash ADC resolution. The second stage is performed with a delta-sigma ADC with a differential input and differential reference. Using the 6-bit flash ADC of novel design and the 24-bit delta-sigma ADC, the nonlinearity error is reduced to 2.6·10−3 %, in the range between −200 °C and 850 °C. Two more ranges are examined, and the following results are obtained: in the range between 0 °C and 500 °C, the nonlinearity error is reduced from 1.99 % to 5·10−4 %, while in the range between −50 °C and 150 °C, the nonlinearity error is reduced from 0.755 % to 2.15·10−4 %.

Electrode Configuration with Howland Current Source and Demodulator for Electrical Impedance Tomography

Abstract Electrical Impedance Tomography (EIT) uses boundary voltage measurements due to multiple injection current patterns to reconstruct cross-sectional impedance images. Usually, the hardware does not provide any capacitive information and the reconstructed image is only based on conductivity. An approach where each electrode has its own Howland current source is a powerful and innovative architecture in which different current injections can be implemented. However, the potential source of error increases with this new architecture when compared with conventional architectures. This paper enumerates some of the potential errors considering the main modules of the electrode: 1. Howland current source; 2. ADC and DAC converters; and 3. The demodulator. A methodology for verifying ADC and DAC precision and linearity is proposed.

Consideration on Input Signal for ADC Histogram Test in Short Time

This paper describes two algorithms for generating test signals to efficiently test the linearity of ADCs. Linearity is an important testing item for ADCs, and it takes a long time (hence is costly) to test especially low-sampling-rate, high-resolution ADCs. We have proposed to generate a test signal consisting of multiple-sine waves, to precisely test the linearity for specific important codes (such as around the center of the output codes), using an arbitrary waveform generator (AWG) and an analog filter in our previous studies. Here, we formulate them for general use. Their verification is performed on a single sine wave, and good results are obtained to show the validity of the derivation algorithm.

Accurate exponential histogram test method for ADC linearity test

An accurate exponential histogram test (EHT) method is proposed for the ADC linearity test. Different from conventional EHT methods which estimate ADC static parameters only based on the number of hits, the proposed method accurately estimates the ADC transition levels, differential non-linearity and integral non-linearity by creative utilisation of the information of stimulus signal. As a result, the proposed method avoids the errors introduced by the assumed proportional relationship between the code width and the number of hits in conventional methods. Simulation results show that the proposed method outperforms the conventional methods in terms of accuracy and robustness.

A 10-bit 100-MS/s Pipelined SAR ADC with Redundancy Generation using Capacitor-based DAC and Linearity-improved Dynamic Amplifier

A 10-bit 100-MS/s pipelined SAR ADC which consists of a 5-bit coarse SAR ADC with 1-bit redundancy, a dynamic amplifier for a residue amplifier, a 6-bit fine SAR ADC, and a digital error correction is proposed. One-bit redundancy generation for a digital error correction is designed using a capacitor-based DAC used in the 5-bit coarse SAR ADC for a sub-ADC of a pipelined ADC. The input range calibration and dynamic amplifier with gain compensation circuit are proposed to improve the linearity of the pipelined SAR ADC. The proposed pipelined SAR ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1.2-V supply voltage. Its active area and power consumption are 410 μm × 425 μm and 4.35 mW, respectively. The measured SNDR are approximately 53.47 dB for a 2.4 VSUBpp/SUB differential sinusoidal input with a frequency of 9.99 MHz.

An ultra low-power DAC with fixed output common mode voltage

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC.

A Low-Power 12-Bit Extended Counting ADC Without Calibration for CMOS Image Sensors

This brief proposes a low-power 12-bit column-parallel extended counting analog-to-digital converter (EC ADC) without calibration for CMOS image sensors. The proposed 12-bit EC ADC uses the ${\Delta \Sigma }$ ADC and single-slope ADC (SS ADC) to convert the input voltage to the upper 4 bit and lower 8 bit, respectively. It reduces power consumption by sharing a comparator between the ${\Delta \Sigma }$ ADC and the SS ADC, and is robust to the inaccurate ramp signal. The 16-LSB linearity error of the ramp signal causes only 1 LSB linearity error of the proposed EC ADC. In addition, the proposed EC ADC improves the ADC linearity without calibration by adjusting the slope of the ramp signal in the lower 8-bit conversion phase according to the capacitance mismatch between the sampling and feedback capacitors. A test chip with 200 readout channels, each including the proposed EC ADC, was fabricated using an 0.18- ${\mu }\text{m}$ CMOS process. The measurement results show that the proposed EC ADC achieves a differential nonlinearity of +0.4/−0.3 LSB and an integral nonlinearity of +3.5/0 LSB without calibration. In addition, the measured signal-to-noise distortion ratio and effective number of bits are 65.4 dB and 10.5-bit, respectively. The measured power consumption per ADC is $22~{\mu }\text{W}$ and the best figure of merit in power efficiency is achieved to be 82 fJ/step.

CFCS calibration circuit design for multi-bit pipelined ADC architectures

Design of high resolution ADCs in scaled CMOS technology is challenging due to increased component mismatch, comparator offset, and finite op-amp gain error. In this work, a commutated feedback capacitor switching calibration technique has been proposed to improve the ENOB and linearity of ADCs with multi-bit pipeline architecture. During normal operation of ADC, the fixed sampling capacitor is swapped in the feedback capacitor. We have distributed the sampling capacitor and swap the feedback capacitor with the sampling capacitor(s) in the MDAC of each pipeline stage ADC. The mismatches of different pipeline stages are concurrently corrected in the digital domain. Proposed technique requires digital calibration circuits and requires no extra calibration phase cycles. The prime objective of this work is to achieve high linearity and ENOB in pipeline architectures with low power consumption. Behavioral simulation of 16-bit 5Ms/s pipeline ADC in UMC 0.18 µm double poly triple metal processes with proposed calibration shows significant improvement in DNL with σ = 0.25% capacitor mismatch with correct 16-bit digital output. The design is implemented using HSPICE simulation. The robustness of the proposed technique has been verified by process, temperature and voltage variation simulations and Monte Carlo analysis.

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to- Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non- binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv. Step which is comparable with existing ADC topologies.

A 10-bit 110 MHz SAR ADC with asynchronous trimming in 65-nm CMOS**Project supported by the Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090105140C09041).

A 10-bit 110 MHz SAR ADC with asynchronous trimming is presented. In this paper, a high linearity sampling switch is used to produce a constant parasitical barrier capacitance which would not change with the range of input signals. As a result, the linearity of the SAR ADC will increase with high linearity sampled signals. Farther more, a high-speed and low-power dynamic comparator is proposed which would reduce the comparison time and save power consumption at the same time compared to existing technology. Additionally, the proposed comparator provides a better performance with the decreasing of power supply. Moreover, a highspeed successive approximation register is exhibited to speed up the conversion time and will reduce about 50% register delay. Lastly, an asynchronous trimming method is provided to make the capacitive-DAC settle up completely instead of using the redundant cycle which would prolong the whole conversion period. This SAR ADC is implemented in 65-nm CMOS technology the core occupies an active area of only 0.025 mm and consumes 1.8 mW. The SAR ADC achieves SFDR > 68 dB and SNDR > 57 dB, resulting in the FOM of 28 fJ/conversion-step. From the test results, the presented SAR ADC provides a better FOM compared to previous research and is suitable for a kind of ADC IP in the design SOC.

Impact of ADC non-linearities on the sensitivity to sterile keV neutrinos with a KATRIN-like experiment

ADC non-linearities are a major systematic effect in the search for keV-scale sterile neutrinos with tritium β-decay experiments like KATRIN. They can significantly distort the spectral shape and thereby obscure the tiny kink-like signature of a sterile neutrino. In this work we demonstrate various mitigation techniques to reduce the impact of ADC non-linearities on the tritium β-decay spectrum to a level of <ppm. The best results are achieved with a multi-pixel (≥104 pixels) detector using full waveform digitization. In this case, active-to-sterile mixing angles of the order of sin2θ=10−7 would be accessible from the viewpoint of ADC non-linearities. With purely peak-sensing ADCs a comparable sensitivity could be reached with highly linear ADCs, sufficient non-linearity corrections or by increasing the number of pixels to ≥105.

Design of a 12-bit 2 MS/s 12 mW pipelined SAR ADC in CMOS 0.18 μm technology for CZT-based imaging system

This paper presents a 12-bit 2 MS/s pipelined successive approximation register (SAR) ADC for CZT-based imaging system. The proposed ADC is divided into a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. The first-stage MDAC has a gain of 16 instead of the usual gain of 64, which considerably minimizes the power dissipation of residue amplifier. The second-stage 8-bit SAR ADC employs unit bridge capacitor split-capacitor architecture aiming to reduce the load capacitance of residue amplifier so as to minimize the power dissipation of the proposed ADC. Moreover, a code-randomized calibration algorithm is proposed to improve the linearity of the second-stage 8-bit split-capacitor SAR ADC. In addition, several radiation-hardened-by-design techniques are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μ m mixed-signal 1.8 V/3.3 V process and occupied a core area of 0.71 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 63.2 dB at 2 MS/s sampling rate and consumes 12 mW power in total. The figure of merit (FoM) of the proposed ADC is 5.06 pJ/conversion-step.