Linearity Metrics Research Articles

Spacer engineering on multi-channel FinFET for advanced wireless applications

Wireless applications require a low power technology that enables DC/analog/RF functions on the same chip. It is well established fact that Multi-channel FinFET (Multifin) enhances the DC/analog/RF performance of the FET. The proposed design with spacer dielectric ensures reduced OFF current (IOFF), better subthreshold performance and improved ON current (ION) towards high performance and low power applications. Along with single-k spacer a dual-k spacer combination of (Air + Si3N4) called hybrid spacer (low-k towards gate and high-k near source/drain) is studied for the first time towards DC/analog/RF and linearity metrics of Multifin FET. The Air spacer shows extravagant performance towards RF domain and HfO2 shows better for DC and analog perspective. With Air spacer dielectric the Multifin FET exhibits terahertz (THz) frequency ranges and ensures high frequency applications. The linearity and harmonic distortion metrics towards wireless communication applications with various spacer dielectric is also analysed. The hybrid spacer shows better linearity and harmonic distortion performance along with Air and shows a strong contender towards RF applications. Moreover, the reduced capacitances ensure hybrid spacer is potential towards driving circuit applications at advanced nodes.

Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide

This paper suggests an analysis of SOI-based GaN FinFET that considers high-k gate oxide into account. The effect of using SOI substrate and a high-k dielectric layer on ON current, OFF current, electric field, electron mobility, conduction & valence band energy, and subthreshold swing is reported. All these parameters are analyzed and compared with bulk GaN FinFET and Si FinFET. We achieve better ON current, faster speed, and more minor subthreshold swing, reducing the short channel effects. A shallow OFF current is obtained because of bulk conduction in the GaN channel area, which the gate can deplete. Several RF/analog metrics are also noted, including transconductance (gm), cut-off frequency (fT), transconductance frequency product (TFP), and transconductance generation factor (TGF), and comparison with Bulk GaN FinFET and Si FinFET is presented. Finally, the linearity metrics like 2nd and 3rd-order voltage intercept points, IIP3, and 1-dB compression point is extracted. Compared to the other two structures, the suggested structure exhibits advantageous DC and RF/analog performances. A comparison of different Figures of Merits (FoMs) for the suggested device with previously published literature is also given.

Measuring non-linearity of multi-session writing processes

When (professional) authors work on their texts, they frequently 'jump' around their document to make textual changes and create new content at a wide range of locations. Currently, a range of linearity measures are available to capture this, some of which requiring time-intensive manual coding. Linearity metrics are commonly calculated based on the leading edge and are mostly used for short texts and single writing sessions. However, especially for longer, multi-session writing processes, text can often be created at various spaces, not necessarily including the leading edge. Accordingly, the leading edge is not enough to distinguish between linear production and non-linear text alterations. Therefore, in the current study, we propose a novel, more flexible, automatized non-linearity analysis, which does not solely rely on the leading edge. In this approach, all backwards and forwards cursor and mouse operations from the point of utterance are extracted from keystroke data, and characterized both based on duration and distance. This results in a detailed list of characteristics per writing episode, allowing us to compare and group episodes of writing at various scales. We illustrate this approach by analysing the writing process of a complete novel based on close to 400 writing sessions totalling 276 h of writing. The results show that the current non-linearity analysis allows us to successfully cluster writing sessions using the non-linearity characteristics. This analysis can be used to find patterns in non-linearity over time, allowing us to chart interactions with the text-produced-so-far and session management strategies in multi-session writing.

Linearity Performance of Derivative Superposition in GaN HEMTs: A Device-to-Circuit Perspective

A significant disconnect exists between the linearity metrics used by device and circuit engineers, degrading the maximum achievable performance in gallium nitride (GaN) technology. A detailed linearity analysis is performed using both device and circuit metrics on GaN devices that employ derivative superposition (DS) to evaluate the amplifier performance under modulated conditions of four different device variants. The limitations of conventional linearity metrics used at the device level, such as the output third-order intercept point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{OI}\text{P}_{\text{3}}$</tex-math> </inline-formula> ) and output 1-dB compression point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{OP}_{\text{1}~\text{dB}}$</tex-math> </inline-formula> ), are examined and compared with communication standard-based metrics, such as the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) to provide best practices for quantifying power amplifier (PA) linearity. It is found that employing more devices in the context of DS primarily improves the input-bias range of the device and not the peak amplifier performance under modulation. Ultimately, this work provides device engineers with a circuit-level perspective on linearity to help design transistors with enhanced RF performance for practical real-world deployment.

Electrochemical Sensor Mediated Assessment of Carbonate Moieties in Soil Matrix

Carbon sequestration is a major global phenomenon that is particularly relevant now with the effect of climate change monitoring and regenerative agriculture. It refers to different practices that contribute to the absorption and storage of carbon in the soil. While the impact of sequestration of carbon is majorly from organic sources, the effect from soil inorganic carbon accumulation is not trivial especially in arid and semi-arid regions where the inorganic carbon (IC) share in sequestration is significant. Movement of Atmospheric Carbon Dioxide (CO2) into soil resources via photosynthesis and root respiration with the subsequent formation of bicarbonate in soil, which exists as bicarbonate in solution phase in groundwater sources or precipitates into CaCO3 in soil phase. Current soil carbon monitoring is either based on extensive soil sampling for analyzing in the laboratory or using proximal sensing methods, which are less accurate. Thus, implementation of novel soil sensors for accurate in-situ measurements could fundamentally improve soil carbon assessment and monitoring. Comparatively, the level and depth of assessing inorganic carbon in soil is significantly lower than that of soil organic carbon (SOC) monitoring. Electrochemistry as a transduction mode is highly viable in this regard due to its ease of applicability in various environments including the complex-soil matrix is a vital component that holds together the Earth’s ecosystem. The key mechanism of releasing the inorganic carbon relies on capturing the different pools that encompass the inorganic/ mineral carbon in soil including- carbonate ions in soil from Calcium (Calcite) which is the major pool of the IC in soil contributing to around 90% of this source and Magnesium (Dolomite). The other minor fraction that is present in the IC pool arises from Bicarbonates (HCO3-).In this sensor development study, we have designed a modified 3-electrode system which is functionalized with a correlated ion-capture film that is functional to changes in carbonate moieties in the soil electrolyte test system. Then this composite sensor was introduced into test soil setups with varying carbonate content to measure the sensor response- wherein, cyclic voltammetry (DC based) and Electrochemical Impedance Spectroscopy was used to determine signal output as a function of increasing dose. It was seen that the peak current around 0.4-0.5V on the positive axis was modulated to increase with carbonate content (% or ppm) and correspondingly- changes in the Rct (charge-transfer resistance) and Zw (Warburg impedance) along with the capacitive element shift was noticeable in the EIS spectra. The experimental cycle was performed using an in-house designed portable potentiostat device which was integrated into a probe head setup that could be inserted into soil for testing. The results from these experiments yielded linearity metrics from regression fits as R2 > 0.97 and measurable sensing range from 0.01% (100 ppm) to 1% (10,000 ppm). Therefore, a first-of-a-kind sensor system was developed for determining carbonate content in real soil samples using an electrochemical mode which will be subsequently tested in-field to survey field deployable and point-of-use capability of the system. Figure 1

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

Temperature plays a decisive role in semiconductor device performance and reliability analysis. The effect is more severe in a negative capacitance (NC) transistor, as the temperature modulates the ferroelectric polarization, implicitly included by the Landau coefficients (α, β, γ) in Technology Computer Aided Design (TCAD) simulations. In this paper, through TCAD simulations, the role of varying ambient temperature is investigated in the linearity and analog/radio-frequency (RF) merits of NC-FinFET. The varying temperature modulates the carrier mobility, the semiconductor bandgap, and the Landau parameter (α). We analyzed the analog/RF and linearity metrics, such as total gate capacitance (C gg), transconductance (g m), unity gain cut-off frequency (f T), the transconductance-frequency product, gain-bandwidth product, higher-order transconductance (g m2 and g m3), voltage intercept points, third-order power intercept and intermodulation points, and 1 dB CP using well-calibrated TCAD models. Our analysis reveals that these parameters are strongly dependent on temperature and the NC span (defined by using S-curve) shrinks with the rise in temperature. Finally, a source follower and three-stage ring oscillator are designed to test the frequency compatibility of the AC simulation for varying temperatures.

Effect of temperature on analog/RF and linearity performance of InSb/Si heterojunction SOI TFET

This work reports the effect of temperature on analog/RF and linearity metrics of pocket doped InSb/Si heterojunction SOI TFET using Silvaco TCAD. In the proposed structure, the conventional SiO2 is replaced with SiO2/HfO2 that suppresses the ambipolar behavior and the n+ pocket introduced towards drain mitigates the effect of field induced quantum confinement which helps to enhance the drain current. The result obtained through simulation shows a better ION/IOFF and average subthreshold swing of 1011 to 107 and 29.3 to 38.5 when temperature varies in the range of 300–400 K. Analog/RF and linearity distortion performance at 400 K have been analyzed in terms of total capacitance, transconductance (2.4 ms/μm), transconductance frequency product (18.62 GHz/V), cutoff frequency (∼600 GHz), gain bandwidth product (5.3THZ), transit time (0.263 ps) and 1dB compression point (-6.6 dB). Reliability analysis shows a significant change in second harmonics with temperature which is unfavorable for subthreshold swing, ambipolar current, and ION/IOFF ratio.

Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

Nonlinear Dynamic RF System Characterization: Envelope Intermodulation Distortion Profiles—A Noise Power Ratio-Based Approach

As radio frequency (RF) applications occupy larger bandwidths, nonlinear dynamics become nonnegligible. This work presents a theoretical framework capable of quantifying the impacts of nonlinear dynamic effects on RF systems through the observation of intermodulation distortion (IMD) profiles produced under multitone excitation. This framework defines static reference profiles and quantifies inband nonlinear dynamic effects as the error between the measured and reference profiles. This analysis demonstrates that classic linearity metrics, such as noise power ratio (NPR), adjacent-channel power ratio, and cochannel power ratio, do not have sufficient frequency resolution to reliably evaluate the impacts of nonlinear dynamics manifested in the IMD profiles produced by broadband RF systems. These observations result in a list of general characterization guidelines to overcome the limitations of classical linearity metrics in the assessment of nonlinear dynamics and the proposal and experimental validation of a novel method, swept-tone NPR, for the characterization of IMD profiles affected by nonlinear dynamic effects. Beyond this, the classic nonlinear dynamic mechanism, responsible for IMD asymmetry, is analyzed under multitone excitation at the system level for the first time, and the limitations of mechanism-based IMD analysis in the presence of nonlinear dynamic effects are evidenced with theoretical examples.

Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire field-effect-transistor (FET) for significantly enhanced performance at sub-5 nm nodes. The symmetric and asymmetric spacer lengths are optimized and compared towards the improvement of subthreshold swing (SS) and switching (IONIOFF) behavior with various spacer dielectrics. For optimal values of source (LS) and drain (LD) spacer lengths, the device IONIOFF ratio has an improvement of 22.69% and a reduction in IOFF by 34.13% as compared to other variations. Our study reveals that, in symmetric spacer variations the device exhibits superior performance with LS=LD=1.5×LG. However, compared to symmetric, the asymmetric spacer exhibits higher IONIOFF and lower SS with LS=1.5×LG and LD=2.5×LG. Moreover, LG scaling impact on SS, DIBL, Vth, and ION are reported with various spacers. The optimized asymmetric spacer exhibits excellent DC characteristics with SS of 64 mV/dec and IONIOFF ratio of ∼108 even for 5 nm gate length (LG) ensures fundamental scaling. At LG of 10 nm with asymmetric spacer, a cut-off frequency (fT) = 0.4 THz, gain-bandwidth product (GBW) = 0.08 THz, and intrinsic delay (τ) = 1.3 ps are achieved. Finally, the device exhibits second order harmonic (gm2) = 0.2 mA/V2 and third order harmonic (gm3) = 1.1 mA/V3 at nano-regime. Thus optimally designed JL nanowire FET ensures potential candidate towards low-power, high frequency, and better linearity for future technology nodes.

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si3N4, HfO2), and hybrid dual-k (Air + Si3N4) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO2) spacer gives a higher switching ratio (ION/IOFF) in the order of ~107, subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO2) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si3N4) outperforms in terms of gain (AV) and output resistance ( R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m 2 , g m 3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

A Comparison of Analog Performance, Linearity, and Distortion Characteristics Between Symmetric InGaAs and Asymmetric InGaAs/InP MOSFETs

In this article, we report an investigation of analog performance, linearity, and harmonic distortion (HD) characteristics for both symmetric and asymmetric InGaAs n-channel MOSFETs at elevated temperatures. Analog performance parameters such as transconductance and voltage gain are found to be better for the asymmetric InGaAs MOSFETs than their symmetric counterparts. The linearity metrics such as g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m2</sub> , g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m3</sub> , voltage intercept points 2 (VIP2), VIP3, IIP3, and third-order intermodulation distortion (IMD3) have been analyzed. Asymmetric devices are found to perform better in terms of linearity. Moreover, distortion is also found to be less for the asymmetric devices than the symmetric ones. A comparison of the linearity and distortion characteristics of InGaAs devices with a similarly sized Si device reveals that, although the Si device performs better in terms of linearity, particularly at elevated temperatures, InGaAs devices have an edge in terms of distortion over the Si device.

A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length

Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless SOI FinFET by different spacer engineering techniques with hafnium based (HfxTi1-xO2) high-k dielectric in the gate stack. The device process parameters like dielectric spacer impact, nano-fin geometry variation, and power analysis along with DC, Analog/RF, and linearity metrics at the nanoscale are investigated. To increase the accuracy of results at lower gate lengths, quantum models are involved by using TCAD simulator. The proposed device shows excellent electrical characteristics with DIBL = 10.6 mV/V, SS = 63.6 mV/dec, switching ratio (ION/IOFF) = ~107 and good ON-OFF performance metric Q = gm/SS = 2.06 × 10−5 S-dec/μm-mV even at 5 nm LG. The performance impact of outer low-k spacer dielectric variation in dual-k spacer reveals that performance enhancement of ~77% in terms of switching ratio, reduction of leakage current by ~73%, and improvement of gm by ~10% have been noticed from SiO2 + HfO2 to Si3N4 + HfO2. However, due to high-k dielectric in dual-k spacer gate capacitances increases, which leads to deterioration of RF parameters like ft, τ, and GBW. The Air single-k spacer shows good performance for RF applications with ft = 600 GHz, τ = 1 ps, GBW = 1.23 THz and dynamic power = 0.095 fJ/μm at LG = 5 nm. However, the linearity characteristics deteriorates for dual-k spacers and higher dielectric single-k spacers (SiO2, Si3N4) has been noticed. This investigation reveals that at nanoscale Air spacer outperforms all other spacer combinations for low power applications and better linearity (low distortion), and assures further scaling for RF applications.

Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

In this paper, we have studied the impact of various dielectric single-k (S-k) and dual-k (D-k) spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric oxide based (HfxTi1−xO2) gate stack to enhance the sub-threshold performance of the device. Performance impact of outer low-k spacer variation on D-k spacer by fixing inner high-k spacer has been reported. In this move, it is noticed that the I ON/I OFF ratio shifted from 8.70 × 105 to 1.30 × 106 which is about ∼1.5x times improvement. Along with DC characteristics, analog/RF and linearity metrics are extracted and analysed. Due to a better gate electrostatic integrity (EI) at an extremely scaled an optimally designed D-k spacer reveals a better DC and analog performance characteristics. The S-k spacer reveals a better performer in power consumption, dynamic power, RF, and linearity characteristics at nano scale. Furthermore, the scaling possibilities by spacers on DC and Analog performance at = 10 nm FinFET with tri-gate geometry at of 7 nm, 5 nm, and 3 nm are also examined. It has been noticed that the enhanced performance with the tri-gate structure is best suitable for future technological nodes.

Band gap and gate metal engineering of novel hetero-material InAs/GaAs-based JLTFET for improved wireless applications

This paper investigates the reliability of a dual metal gate-hetero-material junctionless tunnel FET (DMG-HJLTFET), by using a novel combination of III–V compound semiconducting materials, $$\mathrm{InAs}$$ (lower bandgap) in the source region and $$\mathrm{GaAs}$$ (higher bandgap) in the channel and drain regions. We applied bandgap engineering and dual material gate engineering to improve the linearity metrics and distortion parameters by optimizing an appropriate lower work function tunnel gate toward the source and higher work function supplementary gate toward the drain and compared all the results with SMG (single metal gate)-HJLTFET and Si-JLTFET. The DMG-HJLTFET showed marked improvements in terms of ION, ION/IOFF, SS, $${g}_{\mathrm{m}}$$ , $${g}_{\mathrm{m}3}$$ , VIP2, VIP3, and 1-dB compression point. The input power, IIP3 of DMG-HJLTFET, is 158% greater than SMG-HJLTFET and is 154.7% greater than Si-JLTFET. The distortion power, IMD3 of DMG-HJLTFET, is 171.8% and 20.5% lower than SMG-HJLTFET and Si-JLTFET, respectively, thereby making it suitable for low-power distortion-free wireless communication systems.

Study of Temperature Effect on Analog/RF and Linearity Performance of Dual Material Gate (DMG) Vertical Super-Thin Body (VSTB) FET

This work presents a simulation study of the influence of temperature on the performance of dual material gate (DMG) vertical super-thin body (VSTB) FET. The introduction of DMG causes a drop in the off-state current (Ioff) by ~99.18% and DIBL by 20%. Drop in the Ioff enhances the on-to-off current ratio (Ion/Ioff) by ~98.85%. A rigorous investigation on temperature dependency of DC, analog/RF, and linearity metrics was carried out. The zero temperature coefficient (ZTC) bias point for the DMG device was observed to be nearly at a gate bias of VG = 0.41 V. Various DC figures of merit (FoM) such as subthreshold swing (SS), Ion/Ioff, and threshold voltage (VT) show improvement with temperature fall. Lowering in temperature also leads to enhanced analog/RF performance by offering superior gm, gd, Cgg, Cgd, maximum fT, maximum GBP, intrinsic delay, TGF, TFP, GFP, and GTFP. However, linearity metrics like gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point show better performance with an increase in temperature.

Physics-based analytic modeling and simulation of gate-induced drain leakage and linearity assessment in dual-metal junctionless accumulation nano-tube FET (DM-JAM-TFET)

Physics-based analytical model is proposed in this paper which analyzes the effect of temperature, channel length and silicon film radius on gate-induced drain leakages (GIDL) in dual-metal junctionless accumulation nano-tube FET (DM-JAM-TFET). Formulation and analysis for electric field, Ez, surface potential and gate-induced drain leakage current, Igidl have been done with the help of appropriate boundary conditions utilized in solving two-dimensional Poisson’s equation. Also, the effect of variation in temperatures at T = 300 K and 500 K, silicon film channel length (L 30 nm and 40 nm) and radius of R = 9 nm and R = 10 nm have been studied. The simulated results seem to be in good compliance with the analytical results. To analyze the applicability of DM-JAM-TFET for RFIC applications, linearity of the aforesaid device has been deeply investigated by comparing DM-JAM-TFET with JAM-GAA and DM-JAM-GAA at channel length, L = 20 nm. The linearity metrics namely gm1, gm2, gm3, VIP2, VIP3, IMD3 and IIP3 have been significantly improved in DM-JAM-TFET making it intermodulation distortion resistant.

Linearity Distortion Analysis of III–V and Si Quadruple Gate Field Effect Transistor (QG-FET) for Analog Applications

In this work, analog and linearity distortion performance of a III–V AlGaN/GaN quadruple gate field effect transistor (III–V QG-FET) has been analyzed and compared with conventional Si QG-FET having identical physical dimensions. Specifically, we investigate the linearity by numerically computing transconductance (gm1), its second and third order derivatives (gm2 and gm3), along-with linearity metrics comprising of third order intermodulation distortion (IMD3), third order input intercept point (IIP3), and extrapolated input voltages (VIP2 and VIP3). The consequences of variations in physical parameters of III–V QG-FET, i.e., channel length, channel height, the thickness of oxide layer, doping concentration, along-with temperature on the linearity metrics parameters, drain current, and threshold voltage are analyzed and compared with Si QG-FET. The gate capacitance and dynamic power dissipation is calculated numerically and compared by performing small signal AC analysis at 1 MHz frequency for III–V and Si QG-FETs. The influence of variations in above mentioned physical parameters is also analyzed on dynamic power dissipation and gate capacitance considering the effects of quantum capacitance in the nanometer regime. The present analysis reveals that in III–V QG-FET, the dynamic power dissipation is considerably reduced than its contender Si QG-FET due to its reduced threshold voltage, and thus it is a more promising candidate for analog and low power dissipation applications.

A new design approach to improve DC, analog/RF and linearity metrics of Vertical TFET for RFIC design

This paper presents a novel design of Vertical Tunnel Field Effect Transistor (VTFET) using work-function engineering. In this work, we investigate the impact of work-function engineering for the enhancement of the metrics such as DC, analog/RF and linearity parameters for the low-power, high-speed and high-frequency applications. Using this concept of device engineering, it is demonstrated that VTFET offers the superior improvement in terms of steeper subthreshold slope, SS=26mV/decade, which results in increase of ON-state current, reduction in DIBL=25mV/V and increment in ratio of ION/IOFF of the order of 1011. Moreover, the appropriate selection of work-function for the source, gate and drain electrodes in metal electrodes work function engineering (MEWE) VTFET deals with the trade-off between analog/RF and linearity parameters. This device offers tremendous results in terms of analog/RF and linearity performance as comparison to conventional VTFET and also overcome the drawbacks like short-channel effects and hot-carrier effects.

Approach to suppress ambipolarity and improve RF and linearity performances on ED‐Tunnel FET

This work reports a dual metal bipolar gate-based electrically doped tunnel field-effect transistor (DMBG-ED-TFET) which overcomes the ambipolarity issue and gives improved radio frequency (RF) and linearity metrics. The formations of n + , p + drain and source regions in this device is performed by applying polarity biases at polarity gate (PG)-1 and PG-2 with 1.2 and −1.2 V. In DMBG-ED-TFET, the gate is alienated into three subdivisions and each subdivision named as tunnel gate (M1), BG (M2) and auxiliary gate (M3) with their respective work functions as ϕ M 1 , ϕ M 2 and ϕ M 3 , respectively. Finally, some existent applications were applied on a proposed device with different possible combinations (work function). Those different possible combinations of work function, the proposed device (DMBG-ED-TFET) gives superior results with ϕ M 1 = ϕ M 3 < ϕ M 2 , where ϕ M 1 is near to source region because to increase the I on current and ϕ M 3 is located near the drain region to overwhelm the ambipolarity. Additionally, the application of work function engineering on the proposed device results in improving the DC characteristics along with analogue/RF and linearity figure of merits (VIP3, IIP3 and IMD3) also discussed.